tag: Moore’s Law

Future Foundry Issues
By Ed Sperling - 13 Jul, 2012 - Comments: 0

Semiconductor Manufacturing & Design talks with Luigi Capodieci, fellow at GlobalFoundries, about EUV, the challenges at 20nm and beyond, and the future of the foundry model. [youtube vid=YXov4y0kpfU] » read more

Experts At The Table: Does 20nm Break System-Level Design?
By Ed Sperling - 28 Jun, 2012 - Comments: 1

By Ann Steffora Mutschler System-Level Design sat down to discuss design at 20nm with Drew Wingard, chief technology officer at Sonics; Kelvin Low, deputy director of product marketing at GlobalFoundries, Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence; and Mike Gianfagna, vice president of marketing at Atr... » read more

Bucket Lists
By Ed Sperling - 26 Jun, 2012 - Comments: 0

At 130nm, the introduction of copper interconnects, 300mm wafers and low-k dielectrics left the entire supply chain breathless. There had never been as many changes at a single process node in the history of semiconductors. At 28nm, the number of changes will pale compared to what’s necessary at 20nm, and that will pale to what’s required at 14nm. But unlike 130nm, when most of those cha... » read more

The Moore’s Law Effect
By Ed Sperling - 04 May, 2012 - Comments: 0

Tensilica CTO Chris Rowen sounds off on the role of DSPs in complex SoCs, the future of Moore's Law and the intersection of "big data" with personalized data in mobile devices. [youtube vid=3H9X0X6eO3Q] » read more

Lithography: How Slow Can We Go?
By Chris Mack - 23 Mar, 2012 - Comments: 0

Moore’s Law has always been about economics:  if we follow the trend of Moore’s Law, we can reduce the cost per function for our integrated circuits, making chips more powerful for the same cost, or making chips of a given capability cheaper.  Historically, cost per function has decreased by about 29% per year, corresponding to a factor of 2 decrease in cost every two years.  There are s... » read more

Margin Call
By Ed Sperling - 03 Feb, 2012 - Comments: 0

Ever since Moore’s Law passed 65nm, the discussion has focused on power versus performance. Do you run a chip faster and hotter, or do you keep performance about the same from one chip to the next and improve battery life. At 28nm and beyond, there are other factors that begin to weigh into this discussion. One is reliability. Can a chip developed at the forefront of Moore’s Law be as re... » read more

Commoditizing Green
By Ed Sperling - 03 Nov, 2011 - Comments: 0

Over the past five decades, Moore’s Law has been a powerful guiding principle for shrinking process geometries and improving performance. But with performance now considered secondary to energy and power efficiency, the same forces that have worked to commoditize performance increases while slashing costs will be applied to saving battery life and drawing less energy from the wall. This i... » read more

Tech Talk: Graphic Headaches
By Ed Sperling - 24 Aug, 2011 - Comments: 0

Nvidia senior vice president of GPU engineering Jonah Alben talks with System-Level Design about the challenges of designing a graphics chip at advanced process nodes. [youtube vid=3Nc77aVH94g] » read more

The Growing Need For A Systems Approach
By Ed Sperling - 28 Jul, 2011 - Comments: 0

By Gabe Moretti Electronic computing systems have gone through an evolutionary cycle since the invention of the mainframe, and the process is continuing. Semiconductor technology, mostly based on CMOS fabrication methods, has enabled an increase in design complexity and device functionality that have revolutionized the world. But 20nm processes may be the last that obey Newtonian physics. T... » read more

Viewing Power Through A Funnel
By Ed Sperling - 21 Jul, 2011 - Comments: 0

If Moore’s Law had a corresponding geometric shape, it would be a funnel. At older nodes, the wider part of the funnel could accommodate a full SoC or ASIC. At advanced nodes, moving further into the funnel, only portions of an SoC will actually be designed and built—mostly the digital logic and memory. Everything from analog portions to standard IP and even non-standard IP will be construc... » read more

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