tag: Movellus

Designing A Better Clock Network
By Ann Mutschler - 13 Oct, 2022 - Comments: 0

Laying the proper clock network architecture foundation makes all the difference for the best performance, power, and timing of a chip, particularly in advanced node SoCs packed with billions of transistors. Each transistor, which acts like a standard cell, needs a clock. An efficient clock network should ensure the switching transistors save power. In today’s advanced nodes, when a design... » read more

Startup Funding: September 2022
By Jesse Allen - 05 Oct, 2022 - Comments: 0

The onshoring and buildout of dozens of fabs, many costing tens of billions of dollars, is beginning to spill over into other areas that are critical for chip manufacturing. Materials, in particular, which often gets little attention outside of chip manufacturing, witnessed a big spike in September 2022. In fact, seven materials companies covered in this report made up more than a third of the ... » read more

IC Architectures Shift As OEMs Narrow Their Focus
By Ed Sperling - 03 Oct, 2022 - Comments: 0

Diminishing returns from process scaling, coupled with pervasive connectedness and an exponential increase in data, are driving broad changes in how chips are designed, what they're expected to do, and how quickly they're supposed to do it. In the past, tradeoffs between performance, power, and cost were defined mostly by large OEMs within the confines of an industry-wide scaling roadmap. Ch... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 23 Sep, 2022 - Comments: 0

Quantum The $3 million Breakthrough Prize in Fundamental Physics was awarded to four pioneers in the field of quantum information. The laureates are Charles H. Bennett, Gilles Brassard, David Deutsch and Peter Shor. Bennett and Brassard were part of the team that proved the usefulness of entanglement, while Deutsch defined the quantum version of a Turing machine. Shor invented the first "clear... » read more

Cutting Clock Costs On The Bleeding Edge Of Process Nodes
By Aakash Jani - 01 Aug, 2022 - Comments: 0

In a recent study done by McKinsey and IDC, we see that physical design and verification costs are increasing exponentially with shrinking transistor sizes. As figure 1 shows, physical design (PD) and pre-silicon verification costs are doubling each process leap. As companies leap from node to leading node, a natural question arises. Why is it becoming harder and more expensive to tapeout a chi... » read more

Bespoke Silicon Redefines Custom ASICs
By Ann Mutschler - 28 Jul, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss bespoke silicon and what's driving that customization with Kam Kittrell, vice president of product management in the Digital & Signoff group at Cadence; Rupert Baines, chief marketing officer at Codasip; Kevin McDermott, vice president of marketing at Imperas; Mo Faisal, CEO of Movellus; Ankur Gupta, vice president and general manager of Siemens... » read more

Near-Threshold Computing Gets A Boost
By Brian Bailey - 25 Jul, 2022 - Comments: 0

Near-threshold computing has long been used for power-sensitive devices, but some surprising, unrelated advances are making it much easier to deploy. While near-threshold logic has been an essential technique for applications with the lowest power consumption, it always has been difficult to use. That is changing, and while it is unlikely to become a mainstream technique, it is certainly bec... » read more

Heterogenous Integration Creating New IP Opportunities
By Brian Bailey - 19 Jul, 2022 - Comments: 0

The design IP market has long been known for constant change and evolution, but the industry trend toward heterogenous integration and chiplets is creating some new challenges and opportunities. Companies wanting to stake out a claim in this area have to be nimble, because there will be many potential standards introduced, and they are likely to change quickly as the industry explores what is r... » read more

Adaptive Clocking: Minding Your P-States And C-States
By Aakash Jani - 23 Jun, 2022 - Comments: 0

Larger processor arrays are here to stay for AI and cloud applications. For example, Ampere offers a 128-core behemoth for hyperscalers (mainly Oracle), while Esperanto integrates almost 10x more cores for AI workloads. However, power management becomes increasingly important with these arrays, and system designers need to balance dynamic power with system latency. As we march year over year, t... » read more

Power Domain Implementation Challenges Escalate
By Ann Mutschler - 20 Jun, 2022 - Comments: 0

The number power domains is rising as chip architects build finer-grained control into chips and systems, adding significantly to the complexity of the overall design effort. Different power domains are an essential ingredient in partitioning of different functions. This approach allows different chips in a package, and different blocks in an SoC, to continue running with just enough power t... » read more

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