tag: Movellus

Squeezing The Margins
By Barry Pangrle - 29 Mar, 2023 - Comments: 0

Back in 2016, we looked at the MediaTek Helio X20, the first Tri-Gear mobile SoC. Tri-Gear is a step beyond ARM’s big.LITTLE concept of using two different cores that have unique power and performance characteristics, by adding a third core. The main advantage to this approach is having more core choices to best run workloads at better energy efficiency and performance operating points. At... » read more

How To Build Resilience Into Chips
By Ed Sperling and Ann Mutschler - 27 Feb, 2023 - Comments: 0

Disaggregating chips into specialized processors, memories, and architectures is becoming necessary for continued improvements in performance and power, but it's also contributing to unusual and often unpredictable errors in hardware that are extremely difficult to find. The sources of those errors can include anything from timing errors in a particular sequence, to gaps in bonds between chi... » read more

Chip Design Shifts As Fundamental Laws Run Out Of Steam
By Ann Mutschler - 31 Oct, 2022 - Comments: 12

Dennard scaling is gone, Amdahl's Law is reaching its limit, and Moore's Law is becoming difficult and expensive to follow, particularly as power and performance benefits diminish. And while none of that has reduced opportunities for much faster, lower-power chips, it has significantly shifted the dynamics for their design and manufacturing. Rather than just different process nodes and half ... » read more

Bespoke Silicon Rattles Chip Design Ecosystem
By Ann Mutschler - 19 Oct, 2022 - Comments: 0

Bespoke silicon developers are shaking up relationships, priorities, and methodologies across the semiconductor industry, creating demand for skills that cross traditional boundaries, and driving new business models that leverage these enormous investments. Bespoke silicon designers today are a rare breed, capable of understanding the unique requirements of a specific domain, as well as a gr... » read more

Designing A Better Clock Network
By Ann Mutschler - 13 Oct, 2022 - Comments: 0

Laying the proper clock network architecture foundation makes all the difference for the best performance, power, and timing of a chip, particularly in advanced node SoCs packed with billions of transistors. Each transistor, which acts like a standard cell, needs a clock. An efficient clock network should ensure the switching transistors save power. In today’s advanced nodes, when a design... » read more

Startup Funding: September 2022
By Jesse Allen - 05 Oct, 2022 - Comments: 0

The onshoring and buildout of dozens of fabs, many costing tens of billions of dollars, is beginning to spill over into other areas that are critical for chip manufacturing. Materials, in particular, which often gets little attention outside of chip manufacturing, witnessed a big spike in September 2022. In fact, seven materials companies covered in this report made up more than a third of the ... » read more

IC Architectures Shift As OEMs Narrow Their Focus
By Ed Sperling - 03 Oct, 2022 - Comments: 0

Diminishing returns from process scaling, coupled with pervasive connectedness and an exponential increase in data, are driving broad changes in how chips are designed, what they're expected to do, and how quickly they're supposed to do it. In the past, tradeoffs between performance, power, and cost were defined mostly by large OEMs within the confines of an industry-wide scaling roadmap. Ch... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 23 Sep, 2022 - Comments: 0

Quantum The $3 million Breakthrough Prize in Fundamental Physics was awarded to four pioneers in the field of quantum information. The laureates are Charles H. Bennett, Gilles Brassard, David Deutsch and Peter Shor. Bennett and Brassard were part of the team that proved the usefulness of entanglement, while Deutsch defined the quantum version of a Turing machine. Shor invented the first "clear... » read more

Cutting Clock Costs On The Bleeding Edge Of Process Nodes
By Aakash Jani - 01 Aug, 2022 - Comments: 0

In a recent study done by McKinsey and IDC, we see that physical design and verification costs are increasing exponentially with shrinking transistor sizes. As figure 1 shows, physical design (PD) and pre-silicon verification costs are doubling each process leap. As companies leap from node to leading node, a natural question arises. Why is it becoming harder and more expensive to tapeout a chi... » read more

Bespoke Silicon Redefines Custom ASICs
By Ann Mutschler - 28 Jul, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss bespoke silicon and what's driving that customization with Kam Kittrell, vice president of product management in the Digital & Signoff group at Cadence; Rupert Baines, chief marketing officer at Codasip; Kevin McDermott, vice president of marketing at Imperas; Mo Faisal, CEO of Movellus; Ankur Gupta, vice president and general manager of Siemens... » read more

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