tag: multi-project wafers

Die-level Thinning and Integrating Route For Singulated MPW Chips Using Both Silicon Sensors and CMOS Devices
By Technical Paper Link - 30 Apr, 2022 - Comments: 0

Abstract "Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a high demand for thin silicon devices for several applications, such as flexible electronics. To address this demand, we study a novel post-processing method on two silicon devices, an el... » read more

Rush Hour On The Technology Roadmap
By Mike Gianfagna - 30 Jan, 2017 - Comments: 0

Starting this week, the International Solid State Circuits Conference (ISSCC) will commence at the Marriott in downtown San Francisco. This prestigious conference showcases the latest semiconductor innovations from around the world. Looking at the advance program, one can’t help but notice a shift in the work presented. The conference theme this year is: “Intelligent Chips for a Smart World... » read more

Changing The World, One Transaction At A Time
By Mike Gianfagna - 23 Oct, 2014 - Comments: 0

It’s the season for foundry seminars. A few weeks ago, eSilicon exhibited at the TSMC Open Innovation Platform event in San Jose. This week, we were at the GLOBALFOUNDRIES Technical Seminar, also in San Jose. I talked with a lot of folks during both events – recited the elevator pitch many times (“who is eSilicon?”). Everybody has attention deficit disorder on a tradeshow floor. Fast ex... » read more

Self-Service Semiconductors
By Mike Gianfagna - 27 Mar, 2014 - Comments: 1

The era of self-service is here. Whether you’re in a restaurant, shopping center, airport or cruising the Web, you have more options than ever to browse, research, choose and transact business with little to no human interaction. Self-service isn’t a new concept. In fact, it’s been around a long time. What is new is the pervasive use of high-tech automation to deliver experiences t... » read more

Week In Review: System-Level Design
By Ed Sperling - 07 Feb, 2014 - Comments: 0

Cadence agreed to buy Forte Design Systems for an undisclosed sum, adding further proof that the market for high-level synthesis and tools that run at higher levels of abstraction is finally hitting its stride. Behind this acquisition is a rising pain level due to increasing complexity in SoCs—IP integration, low power concerns and much more of everything, from transistors to memories—has f... » read more

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