One-On-One: Aaron Thean

By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

Manufacturing Bits: July 8

By Mark LaPedus - 08 Jul, 2014 - Comments: 1

Intel foundry deal At the Semicon West trade show in San Francisco, Intel announced that it has entered into a foundry agreement with Panasonic’s LSI Business Division. Intel's custom foundry business will manufacture future Panasonic system-on-chips (SoCs) using Intel's 14nm low-power manufacturing process. Intel’s low-power process will be a derivative of its general-purpose 14nm proc... » read more

VLSI Kyoto – The SOI Papers

By Various Writers - 19 Jun, 2013 - Comments: 0

By Adele Hars There were some breakthrough FD-SOI and other excellent SOI-based papers that came out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14, 2013). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both were presented in “Jumbo Joint Focus” sessions. The papers should all b... » read more

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tag: nanowire

One-On-One: Aaron Thean

Manufacturing Bits: July 8

VLSI Kyoto – The SOI Papers