Research Bits: December 5


Neuromorphic nanowires Researchers from UCLA and University of Sydney built an experimental computing system physically modeled after the biological brain. The device is composed of a tangled-up network of wires containing silver and selenium that were allowed to self-organize into a network of entangled nanowires on top of an array of 16 electrodes. The nanowire network physically reconfigure... » read more

What Designers Need To Know About GAA


While only 12 years old, finFETs are reaching the end of the line. They are being supplanted by gate-all-around (GAA), starting at 3nm [1], which is expected to have a significant impact on how chips are designed. GAAs come in two main flavors today — nanosheets and nanowires. There is much confusion about nanosheets, and the difference between nanosheets and nanowires. The industry still ... » read more

Vertical Nanowire Gate-All-Around FETs based on the GeSn-Material System Grown on Si


A new technical paper titled "Vertical GeSn nanowire MOSFETs for CMOS beyond silicon" was published by researchers at Peter Grünberg Institute 9, JARA, RWTH Aachen University, CEA, LETI, University of Grenoble Alpes, University of Leeds, and IHP. "Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transcon... » read more

Technique For Printing Electronic Circuits Onto Curved & Corrugated Surfaces Using Metal Nanowires (NC State)


A technical paper titled "Curvilinear soft electronics by micromolding of metal nanowires in capillaries" was published by researchers at North Carolina State University. “We’ve developed a technique that doesn’t require binding agents and that allows us to print on a variety of curvilinear surfaces,” says Yuxuan Liu, first author of the paper and a Ph.D. student at NC State in this ... » read more

Phononic and Magnonic Properties of 1D MoI3 Nanowires


A new technical paper titled "Elemental excitations in MoI3 one-dimensional van der Waals nanowires" was published by researchers at NIST, UC Riverside, University of Georgia, Theiss Research Inc, and Stanford University. "We described here the elemental excitations in crystals of MoI3 a vdW [van der Waals] material with a true-1D crystal structure. Our measurements reveal anomalous temperat... » read more

3D Racetrack Memory Device (Max Planck)


A new technical paper titled "Three-dimensional racetrack memory devices designed from freestanding magnetic heterostructures" was published by researchers at Max Planck Institute of Microstructure Physics in Halle, Germany. "Magnetic racetrack memory encodes data in a series of magnetic domain walls that are moved by current pulses along magnetic nanowires. To date, most studies have focuse... » read more

Highly Dense And Vertically Aligned Sub-5 nm Silicon Nanowires


A new technical paper titled "Catalyst-free synthesis of sub-5 nm silicon nanowire arrays with massive lattice contraction and wide bandgap" was published by researchers at Northeastern University, Korea Institute of Science and Technology, Gyeongsang National University and others. "Here, we prepare highly dense and vertically aligned sub-5 nm silicon nanowires with length/diameter aspect r... » read more

Effects of Size Scaling and Device Architecture on the Radiation Response of Nanoscale MOS Transistors


A new technical paper titled "Perspective on radiation effects in nanoscale metal–oxide–semiconductor devices" was published by a researcher at Vanderbilt University, Nashville, Tennessee. The work was partially supported by the Defense Threat Reduction Agency and by the U.S. Air Force Office of Scientific Research and Air Force Research Laboratory. According to the paper, "this Perspect... » read more

Ultra-Fast Photonic Computing Using Polarization


New technical paper titled "Polarization-selective reconfigurability in hybridized-active-dielectric nanowires" was recently published by researchers at University of Oxford and University of Exeter.  The paper demonstrates "the ability to use polarization as a parameter to selectively modulate the conductance of individual nanowires within a multi-nanowire system. By using polarization as the... » read more

Define & Grow III–V Vertical Nanowires At A High Footprint Density on a Si Platform


New technical paper titled "Directed Self-Assembly for Dense Vertical III–V Nanowires on Si and Implications for Gate All-Around Deposition" is published from researchers at Lund University in Sweden. Abstract: "Fabrication of next generation transistors calls for new technological requirements, such as reduced size and increased density of structures. Development of cost-effective proc... » read more

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