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Phononic and Magnonic Properties of 1D MoI3 Nanowires


A new technical paper titled "Elemental excitations in MoI3 one-dimensional van der Waals nanowires" was published by researchers at NIST, UC Riverside, University of Georgia, Theiss Research Inc, and Stanford University. "We described here the elemental excitations in crystals of MoI3 a vdW [van der Waals] material with a true-1D crystal structure. Our measurements reveal anomalous temperat... » read more

3D Racetrack Memory Device (Max Planck)


A new technical paper titled "Three-dimensional racetrack memory devices designed from freestanding magnetic heterostructures" was published by researchers at Max Planck Institute of Microstructure Physics in Halle, Germany. "Magnetic racetrack memory encodes data in a series of magnetic domain walls that are moved by current pulses along magnetic nanowires. To date, most studies have focuse... » read more

Highly Dense And Vertically Aligned Sub-5 nm Silicon Nanowires


A new technical paper titled "Catalyst-free synthesis of sub-5 nm silicon nanowire arrays with massive lattice contraction and wide bandgap" was published by researchers at Northeastern University, Korea Institute of Science and Technology, Gyeongsang National University and others. "Here, we prepare highly dense and vertically aligned sub-5 nm silicon nanowires with length/diameter aspect r... » read more

Effects of Size Scaling and Device Architecture on the Radiation Response of Nanoscale MOS Transistors


A new technical paper titled "Perspective on radiation effects in nanoscale metal–oxide–semiconductor devices" was published by a researcher at Vanderbilt University, Nashville, Tennessee. The work was partially supported by the Defense Threat Reduction Agency and by the U.S. Air Force Office of Scientific Research and Air Force Research Laboratory. According to the paper, "this Perspect... » read more

Ultra-Fast Photonic Computing Using Polarization


New technical paper titled "Polarization-selective reconfigurability in hybridized-active-dielectric nanowires" was recently published by researchers at University of Oxford and University of Exeter.  The paper demonstrates "the ability to use polarization as a parameter to selectively modulate the conductance of individual nanowires within a multi-nanowire system. By using polarization as the... » read more

Define & Grow III–V Vertical Nanowires At A High Footprint Density on a Si Platform


New technical paper titled "Directed Self-Assembly for Dense Vertical III–V Nanowires on Si and Implications for Gate All-Around Deposition" is published from researchers at Lund University in Sweden. Abstract: "Fabrication of next generation transistors calls for new technological requirements, such as reduced size and increased density of structures. Development of cost-effective proc... » read more

Hybrid Sensing Platform w/Silicon Nanowires on a Fully Functional CMOS Chip Containing the Readout Electronics & Signal amplification


New technical paper titled "Multisite Dopamine Sensing With Femtomolar Resolution Using a CMOS Enabled Aptasensor Chip" from TU Dresden, Riken Quantitative Biological Center, Imperial College London, NaMLab gGmbH, ETH Zürich, MaxWell Biosystems AG, TU Wien, and Institute of Radiopharmaceutical Cancer Research. Abstract "Many biomarkers including neurotransmitters are found in external bo... » read more

The resurrection of tellurium as an elemental two-dimensional semiconductor


Abstract "The graphene boom has triggered a widespread search for novel elemental van der Waals materials thanks to their simplicity for theoretical modeling and easy access for material growth. Group VI element tellurium is an unintentionally p-type doped narrow bandgap semiconductor featuring a one-dimensional chiral atomic structure which holds great promise for next-generation electronic, ... » read more

Label-Free C-Reactive Protein Si Nanowire FET Sensor Arrays With Super-Nernstian Back-Gate Operation


Abstract: "We present a CMOS-compatible double gate and label-free C-reactive protein (CRP) sensor, based on silicon on insulator (SOI) silicon nanowires arrays. We exploit a reference subtracted detection method and a super-Nernstian internal amplification given by the double gate structure. We overcome the Debye screening of charged CRP proteins in solutions using antibodies fragments as c... » read more

High Electron Mobility in Strained GaAs Nanowires


Abstract: "Transistor concepts based on semiconductor nanowires promise high performance, lower energy consumption and better integrability in various platforms in nanoscale dimensions. Concerning the intrinsic transport properties of electrons in nanowires, relatively high mobility values that approach those in bulk crystals have been obtained only in core/shell heterostructures, where elec... » read more

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