5G Needs Cohesive Pre- And Post-Silicon Verification

By Jean-Marie Brunet - 24 Oct, 2019 - Comments: 1

While 5G doesn’t start from a clean slate, it does make significant changes to the 4G architecture. These changes mean that the ecosystem from chips to operators is evolving, giving opportunities to more companies to engage in this growing market. Realignment in fronthaul, midhaul and backhaul In particular, the radio access network (RAN) has been redefined as Cloud RAN (sometimes called ... » read more

Xceler Systems: Graph Architecture

By Kevin Fogarty - 19 Mar, 2018 - Comments: 0

An inventor who made foundational contributions to three key ways we move data through complex systems is developing a new type of neuromorphic chip to accelerate AI applications. Rather than try to build a computer that looks like a brain, Gautam Kavipurapu and Xceler Systems are building smaller bits that act like synapses. When the design is advanced enough and there are enough of them, t... » read more

Mobile Edge Computing For The IoE

By Ernest Worthman - 07 Apr, 2016 - Comments: 0

More attention is being focused on the edges of networks as the IoE begins taking hold. The reason is that the current wireless infrastructure is inadequate for handling the billions of endpoints that will make up the IoE. So for the IoE to realize its full potential, it will either require some sort of add-on infrastructure or a new discovery in physics. Edge networks were not always suc... » read more

Virtualizing Cloud Computing With Optimized IP For NFV SoCs

By Synopsys - 13 May, 2015 - Comments: 0

The growth in Internet traffic is impacting how cloud and carrier data center operators design their compute and data networking architectures. To meet the application demands for scale-out servers and networks, designers are implementing virtual environments such as Network Function Virtualization (NFV) to achieve higher efficiency and lower the cost and time of deploying the new applications.... » read more

Blog Review: Dec. 3

By Ed Sperling - 03 Dec, 2014 - Comments: 0

Mentor's Robin Bornoff zeroes in on some of the biggest and most frustrating causes of energy loss—the ones that have nothing to do with the intended task. In electronics, it's a question of how much power is consumed pushing around electrons and photons. Cadence's Richard Goering follows a panel discussion about whether we're really making progress in low-power design, where the challeng... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: network function virtualization

5G Needs Cohesive Pre- And Post-Silicon Verification

Xceler Systems: Graph Architecture

Mobile Edge Computing For The IoE

Virtualizing Cloud Computing With Optimized IP For NFV SoCs

Blog Review: Dec. 3