Hardware Security for Silicon Photonic-Based AI Accelerators


A technical paper titled “Integrated Photonic AI Accelerators under Hardware Security Attacks: Impacts and Countermeasures” was published by researchers at Ecole Polytechnique de Montreal and Colorado State University. Abstract: "Integrated photonics based on silicon photonics platform is driving several application domains, from enabling ultra-fast chip-scale communication in high-perfor... » read more

Neural Architecture & Hardware Accelerator Co-Design Framework (Princeton/ Stanford)


A new technical paper titled "CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework" was published by researchers at Princeton University and Stanford University. "Recently, automated co-design of machine learning (ML) models and accelerator architectures has attracted significant attention from both the industry and academia. However, most co-design frameworks either... » read more

Re-Imagining The GPU


John Rayfield, CTO at Imagination Technologies, sat down with Semiconductor Engineering to talk about RISC-V, AI, and computing architectures. What follows are excerpts of that conversation. SE: What your plans are for RISC-V? Rayfield: We're actively finalizing the integration of RISC-V cores into future-generation GPUs. That work has been going on for several months. Moving forward, we'... » read more