Hybrid architecture based on two-dimensional memristor crossbar array and CMOS integrated circuit for edge computing


Abstract "The fabrication of integrated circuits (ICs) employing two-dimensional (2D) materials is a major goal of semiconductor industry for the next decade, as it may allow the extension of the Moore’s law, aids in in-memory computing and enables the fabrication of advanced devices beyond conventional complementary metal-oxide-semiconductor (CMOS) technology. However, most circuital demons... » read more

Is Programmable Overhead Worth The Cost?


Programmability has fueled the growth of most semiconductor products, but how much does it actually cost? And is that cost worth it? The answer is more complicated than a simple efficiency formula. It can vary by application, by maturity of technology in a particular market, and in the context of much larger systems. What's considered important for one design may be very different for anothe... » read more

Always-On DSPs


There are tradeoffs between powering circuits down to save power and waking them up to respond to voice and visual commands. Prakash Madhvapathy, director of product marketing and product management at Cadence, talks about the best ways to deploy digital signal processors, why multiple DSPs are often better than just one, and what penalties there are for various approaches. » read more

Power/Performance Bits: Dec. 14


Improved digital sensing Researchers from Imperial College London and Technical University of Munich propose a technique to improve the capability of many different types of sensors. The method addresses voltage limits in analog-to-digital converters and the saturation that results in poor quality when an incoming signal exceeds those limits. “Our new technique lets us capture a fuller ra... » read more

Gaps In The AI Debug Process


When an AI algorithm is deployed in the field and gives an unexpected result, it's often not clear whether that result is correct. So what happened? Was it wrong? And if so, what caused the error? These are often not simple questions to answer. Moreover, as with all verification problems, the only way to get to the root cause is to break the problem down into manageable pieces. The semico... » read more

Solving Real World AI Productization Challenges With Adaptive Computing


The field of artificial intelligence (AI) moves swiftly, with the pace of innovation only accelerating. While the software industry has been successful in deploying AI in production, the hardware industry – including automotive, industrial, and smart retail – is still in its infancy in terms of AI productization. Major gaps still exist that hinder AI algorithm proof-of-concepts (PoC) from b... » read more

Getting Better Edge Performance & Efficiency From Acceleration-Aware ML Model Design


The advent of machine learning techniques has benefited greatly from the use of acceleration technology such as GPUs, TPUs and FPGAs. Indeed, without the use of acceleration technology, it’s likely that machine learning would have remained in the province of academia and not had the impact that it is having in our world today. Clearly, machine learning has become an important tool for solving... » read more

How Dynamic Hardware Efficiently Solves The Neural Network Complexity Problem


Given the high computational requirements of neural network models, efficient execution is paramount. When performed trillions of times per second even the tiniest inefficiencies are multiplied into large inefficiencies at the chip and system level. Because AI models continue to expand in complexity and size as they are asked to become more human-like in their (artificial) intelligence, it is c... » read more

Configuring AI Chips


Change is almost constant in AI systems. Vinay Mehta, technical product marketing manager at Flex Logix, talks about the need for flexible architectures to deal with continual modifications in algorithms, more complex convolutions, and unforeseen system interactions, as well as the ability to apply all of this over longer chip lifetimes. Related Dynamically Reconfiguring Logic A differ... » read more

Why Reconfigurability Is Essential For AI Edge Inference Throughput


For a neural network to run at its fastest, the underlying hardware must run efficiently on all layers. Through the inference of any CNN—whether it be based on an architecture such as YOLO, ResNet, or Inception—the workload regularly shifts from being bottlenecked by memory to being bottlenecked by compute resources. You can think of each convolutional layer as its own mini-workload, and so... » read more

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