System-Aware SoC Power, Noise And Reliability Signoff


In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

Transient Current Crunch


When Intel talks, people listen. So when Intel executive VP Dadi Perlmutter said in a keynote at ISSCC in 2012 that transient power noise was one of the most limiting aspects of the chip design process—and how the package and the board inductance are limiting how low they can take the supply voltage—it showed the gravity of the challenge of effectively managing transient power. Transient po... » read more

The Deafening Problem Of High-Speed I/O


By Ann Steffora Mutschler The performance of digital systems today is limited by the interconnection bandwidth between chips, boards, and cabinets. This has driven I/O speeds up into the gigabytes. While this boosts performance, it also opens the door to a host of new problems within the chip, board and system. Add low-power requirements to the mix and it is a recipe for huge headaches. One... » read more

Changing Opinions About Noise


By Brian Fuller On a sunny, warm May day in 2009, NIST researcher Jason Campbell took the stage at an IEEE event in Austin with a presentation that was sure cast a pall over the booming low-power semiconductor world. Campbell’s paper, written with Liangchun Yu, Kin Cheung, Jin Qin, John S. Suehle, A. Oates, Kuang Sheng, was entitled “Large Random Telegraph Noise in Sub-Threshold Opera... » read more

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