tag: NPU

A New Era For Co-Processing
By Brian Bailey - 09 Apr, 2026 - Comments: 0

Key Takeaways: There is no single processor capable of executing everything efficiently, meaning that multiple processors are required. Maximum efficiency is gained by minimizing the movement of data. Architects must maximize efficiency for today's workloads, while also adding enough flexibility to handle tomorrow's. New processor architectures are rapidly evolving thanks to... » read more

State Of The Market For Edge Silicon
By Ed Sperling - 08 Apr, 2026 - Comments: 0

The explosion of data and the rapid ramp of AI is causing significant changes in how chips are architected. At the edge, the key metrics are power, latency, and performance, but those can vary significantly by application and by workload. Steve Roddy, chief marketing officer at Quadric, talks about the need to balance performance and efficiency with flexibility for different applications, what ... » read more

Changes In Chip Architectures At The Edge
By Ed Sperling - 04 Feb, 2026 - Comments: 0

Edge computing is all about low latency, within a tight power budget, and with sufficient performance. This is very different from an AI data center, where the real focus is on data throughput between processor and memory. Achieving those goals requires a focus on what different processing elements bring to the table. Nigel Drego, co-founder and CTO of Quadric, talks about how these different c... » read more

Addressing Critical Tradeoffs In NPU Design
By Ann Mutschler - 21 Jan, 2026 - Comments: 1

Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven W... » read more

How And Why To Optimize NPUs
By Ann Mutschler - 15 Jan, 2026 - Comments: 0

Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones.  Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven... » read more

Study Of HW Acceleration for Neural Networks (Arizona State Univ.)
By Technical Paper Link - 02 Jan, 2026 - Comments: 0

A new technical paper titled "Hardware Acceleration for Neural Networks: A Comprehensive Survey" was published by researchers at Arizona State University. Abstract "Neural networks have become a dominant computational workload across cloud and edge platforms, but their rapid growth in model size and deployment diversity has exposed hardware bottlenecks that are increasingly dominated by mem... » read more

AI Moves Out Of The Cloud And Onto The Edge
By Lee Vick - 11 Dec, 2025 - Comments: 0

The impact of AI to date, in the cloud, is undisputed, but the question we must answer going forward is whether we can only expect more of the same or whether there is a fundamental shift looming that will change everything. Today, we will explore historical data to find patterns repeated through the ages to help us see what I will attempt to prove is imminent. A brief history of time… keepi... » read more

Next Generation AI: Transitioning Inference From The Cloud To The Edge
By Paul Karazuba - 11 Dec, 2025 - Comments: 0

AI inference deployments are increasingly focused on the edge as manufacturers seek the consistent latency, enhanced privacy, and reduced operational costs they can’t achieve in cloud-based deployments. While cloud-based platforms provide incredible computational power and enable widely adopted services, the dependence on network connectivity inherently creates variability, cost and security ... » read more

Next Generation AI: Transitioning Inference from the Cloud to the Edge
By Expedera - 10 Dec, 2025 - Comments: 0

Deploying AI inference at the edge—on smartphones, appliances, industrial devices, and vehicles—promises faster, private, and energy-efficient intelligence. Expedera’s packet-based NPU architecture delivers up to 90% utilization and dramatic reductions in memory movement compared to conventional approaches, enabling next-generation real-time AI capabilities. This white paper examines tech... » read more

ONNX And Python To C++: State-Of-The-Art Graph Compilation
By Quadric.io - 15 Oct, 2025 - Comments: 0

Nigel Drego, Co-founder and Chief Technology Officer at Quadric, presented the “ONNX and Python to C++: State-of-the-art Graph Compilation” tutorial at this year's Embedded Vision Summit. Quadric’s Chimera general-purpose neural processor executes complete AI/ML graphs—all layers, including pre- and post-processing functions traditionally run on separate DSP processors. Read more here. » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy