Uncertainty, But Not Over Power

The semiconductor industry has reached a crossroads. Lithography has stalled out, NRE is rising, and chipmakers are torn between choices of when and whether to jump to the next process node—and even more daunting, the next one after that—or whether to take half steps with fan outs, 2.5D, or fully depleted SOI. While chips do continue to tape out, the number of critical choices that need... » read more

Uncertainty Increases About What’s Next

Across the semiconductor industry, there is a lot of talk about what’s next. Lithography advances have stalled, NRE and mask costs are rising, and complexity is exploding. But unlike the 1 micron wall, which was supposed to be impenetrable, there is no single issue holding back progress. Instead, there are lots of them, most with pricey workarounds, but which together become more complicat... » read more

New Pain And Inflection Points

Jack Harding, CEO of eSilicon, talks with Semiconductor Engineering about the explosion in the costs and the risk of semiconductor designs at the leading edge of Moore's Law. [youtube vid=HLS5QhnGHfM] » read more

New Math: 1+1=1?

From the standpoint of place and route, synthesis, and even some pieces of the hardware verification, the cost of chips even at advanced nodes hasn’t budged. It’s now possible to create a chip at 28nm with roughly the same budget as a 40nm chip, and inside many companies that’s what the hardware engineering manager sees. Look across the entire SoC design chain, however, and the picture... » read more

A Well-Engineered Leap Of Faith

The economics of engineering chips are changing again. We’ve been hearing for several process nodes about runaway non-recurring engineering costs and the rising costs of masks and how Moore’s Law would meet an abrupt end because no one could afford to stay the course. And while it’s true that not everyone did stay the course, the solution has turned out less onerous than many predi... » read more

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