Spiking Neural Networks: Hardware & Algorithm Developments


A new technical paper titled "Exploring Neuromorphic Computing Based on Spiking Neural Networks: Algorithms to Hardware" was published by researchers at Purdue University, Pennsylvania State University, and Yale University. Excerpt from Abstract: "In this article, we outline several strides that neuromorphic computing based on spiking neural networks (SNNs) has taken over the recent past, a... » read more

Ferroelectric Polarization in an Elementary Substance or Single-Element Compound


A technical paper titled "Two-dimensional ferroelectricity in a single-element bismuth monolayer" was published by researchers at National University of Singapore, Zhejiang University, Tianjin University, and University of Chinese Academy of Sciences. Abstract "Ferroelectric materials are fascinating for their non-volatile switchable electric polarizations induced by the spontaneous inversi... » read more

New Spintronics Manufacturing Process, Allowing Scaling Down To Sub-5nm (U. of Minnesota/NIST)


A new technical paper titled "Sputtered L10-FePd and its Synthetic Antiferromagnet on Si/SiO2 Wafers for Scalable Spintronics" was published by researchers at University of Minnesota and NIST, with funding by DARPA and others. According to a University of Minnesota summary news article, "The industry standard spintronic material, cobalt iron boron, has reached a limit in its scalability. The... » read more

Shift Register-In-Memory Architecture


A new technical paper titled "Toward Single-Cell Multiple-Strategy Processing Shift Register Powered by Phase-Change Memory Materials" was published by researchers at Singapore University of Technology and Design and University of Cambridge. Abstract "Modern innovations are built on the foundation of computers. Compared to von Neumann architectures having separate storage and processing uni... » read more

Co-Design View of Cross-Bar Based Compute-In-Memory


A new review paper titled "Compute in-Memory with Non-Volatile Elements for Neural Networks: A Review from a Co-Design Perspective" was published by researchers at Argonne National Lab, Purdue University, and Indian Institute of Technology Madras. "With an over-arching co-design viewpoint, this review assesses the use of cross-bar based CIM for neural networks, connecting the material proper... » read more

Rowhammer: Recent Developments & Future Directions (ETH Zurich)


A new technical paper titled "Fundamentally Understanding and Solving RowHammer" was published by researchers at ETH Zurich. Abstract: "We provide an overview of recent developments and future directions in the RowHammer vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which are used in almost all computing systems as main memory. RowHammer is the phenomenon i... » read more

Research Bits: Aug. 8


Speeding NVM encryption Researchers from North Carolina State University propose a way to speed up encryption and file system performance for non-volatile memory (NVM). “NVMs are an emerging technology that allows rapid access to the data, and retains data even when a system crashes or loses power,” said Amro Awad, an assistant professor of electrical and computer engineering at North C... » read more

Edge-AI Hardware for Extended Reality


New technical paper titled "Memory-Oriented Design-Space Exploration of Edge-AI Hardware for XR Applications" from researchers at Indian Institute of Technology Delhi and Reality Labs Research, Meta. Abstract "Low-Power Edge-AI capabilities are essential for on-device extended reality (XR) applications to support the vision of Metaverse. In this work, we investigate two representative XR w... » read more

What’s In A Name(space)? Optimizing SSD Controller Performance And Verification


Solid state drives (SSDs) have come to the forefront as a promising solution for today and tomorrow’s immense data transfer and storage demands. And SSDs themselves are constantly evolving with upgrades of their critical components to provide higher access speeds. One such component for the NVMe specification is created by the division of non-volatile memory (NVM) into what are commonly known... » read more

Memory Bandwidth Regulation on Hybrid NVM/DRAM Platforms


New technical paper from Shanghai Jiao Tong University Abstract "Non-volatile memory (NVM) has emerged as a new memory media, resulting in a hybrid NVM/DRAM configuration in typical servers. Memory-intensive applications competing for the scant memory bandwidth can yield degraded performance. Identifying the noisy neighbors and regulating the memory bandwidth usage of them can alleviate th... » read more

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