Memory Bandwidth Regulation on Hybrid NVM/DRAM Platforms

Researchers present comprehensive system to regulate memory bandwidth on the hybrid NVM/DRAM platforms.


New technical paper from Shanghai Jiao Tong University

“Non-volatile memory (NVM) has emerged as a new memory media, resulting in a hybrid NVM/DRAM configuration in typical servers. Memory-intensive applications competing for the scant memory bandwidth can yield degraded performance. Identifying the noisy neighbors and regulating the memory bandwidth usage of them can alleviate the contention and achieve better performance. This paper finds that bandwidth competition is more severe on hybrid platforms and can even significantly degrade the total system bandwidth. Besides the absolute bandwidth, the competition is also highly correlated with the bandwidth type. Unfortunately, NVM and DRAM share the same memory bus, and their traffic is mixed together and interferes with each other, making memory bandwidth regulation a challenge on hybrid NVM/DRAM platforms.

This paper first presents an analysis of memory traffic interference and then introduces MT2 to regulate memory bandwidth among concurrent applications on hybrid NVM/DRAM platforms. Specifically, MT2 first detects memory traffic interference and monitors different types of memory bandwidth of applications from the mixed traffic through hardware monitors and software reports. MT2 then leverages a dynamic bandwidth throttling algorithm to regulate memory bandwidth with multiple mechanisms. To expose such a facility to applications, we integrate MT2 into the cgroup mechanism by adding a new subsystem for memory bandwidth regulation. The evaluation shows that MT2 can accurately identify the noisy neighbors, and the regulation on them allows other applications to improve performance by up to 2.6× compared to running with unrestricted noisy neighbors.”

Find the open access technical paper here. Presented in Feb. 2022 at the USENIX Conference on File and Storage Technologies. Related slides can be found here.

Jifei Yi, Benchao Dong, Mingkai Dong, Ruizhe Tong, and Haibo Chen, Institute of Parallel and Distributed Systems, Shanghai Jiao Tong University.

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