Bringing Curvilinear Data To Mask Data Prep

By Al Blais - 15 Aug, 2024 - Comments: 0

Advanced nodes that have been leveraging curvilinear correction with technologies such as ILT and curvilinear OPC are increasingly requiring the use of curvilinear masks to meet advanced feature size and pitch requirements. However, building curvilinear masks with standard OASIS file formats can come at the cost of large file sizes, increased turnaround time, and reduced quality of results. The... » read more

The Quest For Curvilinear Photomasks

By Mark LaPedus - 15 Apr, 2021 - Comments: 1

The semiconductor industry is making noticeable progress on the development of advanced curvilinear photomasks, a technology that has broad implications for chip designs at the most advanced nodes and the ability to manufacture those chips faster and cheaper. The question now is when will this technology move beyond its niche-oriented status and ramp up into high-volume manufacturing. For ye... » read more

Optimizing Tool Integration Is Essential To Design Success

By James Paris - 22 Dec, 2020 - Comments: 0

By James Paris and Armen Asatryan The relationship between a place and route (P&R) application and the collection of system-on-chip (SoC) design implementation, analysis, and verification methodologies and tools has always been very much a two-way street. The P&R system is the base, if you will, of design implementation—it takes the virtual and makes it physical. However, it is use... » read more

Week in Review: IoT, Security, Autos

By Jeff Dorsch And Susan Rambo - 18 Oct, 2019 - Comments: 0

Products/Services The Networking for Autonomous Vehicles Alliance announces that Marvell Semiconductor is joining the NAV Alliance following its acquisition of Aquantia. Fourteen companies are in the industry organization, including Bosch, Continental, Nvidia, and Volkswagen. “The NAV Alliance is developing the platforms that will create the future of transportation and we believe that Multi... » read more

IIoT Grows, But So Do Risks

By Jeff Dorsch - 04 May, 2017 - Comments: 1

By Jeff Dorsch & Ed Sperling After years of fitful progress, [getkc id="78" kc_name="Industrial Internet of Things"] technology is gaining adoption on the factory floor, in the electrical power grid, and other areas that could do with greater amounts of data analysis and insights from a connected ecosystem. AT&T, General Electric, IBM, Verizon Communications, and other large ... » read more

Rule Deck Comparison Doesn’t Have To Be Difficult

By Saunder Peng - 22 Jan, 2015 - Comments: 0

Foundry rule decks change all the time, as foundries uncover new manufacturing issues, or the process changes, or design criteria are tightened to improve runtime or stability. Sometimes new versions of a user’s design rule checking (DRC) tool are released, and the results from the DRC run differ from the previous version. Or perhaps a company wants to compare results between rule decks from ... » read more

Deployment of OASIS In The Semiconductor Industry

By Various Writers - 19 Mar, 2014 - Comments: 0

The OASIS working group was first initiated in 2001, published the new format in March 2004, which was ratified as an official SEMI standard in September 2005. A follow-on initiative expanded the new standard to cover the needs of the mask manufacturing equipment sector with a derived standard called OASIS.MASK (P44) that was released in November 2005 and updated in May 2008. While there are ma... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer