Chip Industry Week In Review

By The SE Staff - 21 Nov, 2025 - Comments: 0

China's Hefei Lumiverse Technology reportedly has developed a desktop-sized High Harmonic Generation light source that generates wavelengths as small as 1nm. One customer already has used it to produce 14nm chips, which was the original target node for EUV, according to one report. As a point of comparison, TSMC and Samsung didn't start using EUV until the 7nm node, relying instead on immersion... » read more

Linear Pluggable Optics Save Energy In Data Centers

By Bryon Moyer - 24 Feb, 2025 - Comments: 0

Linear pluggable optics (LPO) is garnering more attention as a way to quickly and efficiently move data in and out of server racks, but a lack of standards for connecting the optical modules is slowing adoption at a time when there is growing pressure to reduce power in data centers. LPO is the newest of two approaches to solving the power wall problem in data centers. Co-packaged optics (CP... » read more

Chip Industry Week In Review

By The SE Staff - 19 Jan, 2024 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan Synopsys will acquire Ansys for about $35 billion in cash and stock. The deal will boost Synopsys' multi-physics simulation capabilities, which are essential for complex 3D-IC designs, where thermal density can have significant repercussions. The acquisition is expected to be finalized in the first half of 2025. Worldwide semiconductor revenue ... » read more

AI Drives Need For Optical Interconnects In Data Centers

By Karen Heyman - 28 Sep, 2023 - Comments: 0

An explosion of data, driven by more sensors everywhere and the inclusion of AI/ML in just about everything, is ratcheting up the pressure on data centers to leverage optical interconnects to speed up data throughput and reduce latency. Optical communication has been in use for several decades, starting with long-haul communications, and evolving from there to connect external storage to ser... » read more

New Standards Push Co-Packaged Optics

By Karen Heyman - 26 Apr, 2023 - Comments: 0

Co-packaged optics (CPOs) promise five times the bandwidth of pluggable connections, but the new architecture requires multiple changes to accommodate different applications. The Optical Internetworking Forum (OIF) recently published standards for co-packaged optics, which are the photonic industry’s hope for handling today’s faster Ethernet interfaces, as well as increasing speeds and p... » read more

1.6 Tb/s Ethernet Challenges

By Ed Sperling - 16 Nov, 2021 - Comments: 0

Moving data at blazing fast speeds sounds good in theory, but it raises a number of design challenges. John Swanson, senior product marketing manager for high-performance computing digital IP at Synopsys, talks about the impact of next-generation Ethernet on switches, the types of data that need to be considered, the causes of data growth, and the size and structure of data centers, both in the... » read more

Many Chiplet Challenges Ahead

By Brian Bailey - 12 Apr, 2021 - Comments: 0

Over the past couple of months, Semiconductor Engineering has looked into several aspects of 2.5D and 3D system design, the emerging standards and steps that the industry is taking to make this more broadly adopted. This final article focuses on the potential problems and what remains to be addressed before the technology becomes sustainable to the mass market. Advanced packaging is seen as ... » read more

Waiting For Chiplet Standards

By Brian Bailey - 25 Mar, 2021 - Comments: 2

The need and desire for chiplets is increasing, but for most companies that shift will happen slowly until proven standards are in place. Interoperability and compatibility depend on many layers and segments of the supply chain coming to agreement. Unfortunately, fragmented industry requirements may lead to a plethora of solutions. Standards always have enabled increasing specialization. ... » read more

Emerging Apps And Challenges For Packaging

By Mark LaPedus - 23 Nov, 2020 - Comments: 0

Advanced packaging is playing a bigger role and becoming a more viable option to develop new system-level chip designs, but it also presents chipmakers with a confusing array of options and sometimes a hefty price tag. Automotive, servers, smartphones and other systems have embraced advanced packaging in one form or another. For other applications, it's overkill, and a simpler commodity pack... » read more

Designs Beyond The Reticle Limit

By Brian Bailey - 12 Nov, 2020 - Comments: 0

Designs continue to grow in size and complexity, but today they are reaching both physical and economic challenges. These challenges are causing a reversal of the integration trend that has provided much of the performance and power gains over the past couple of decades. The industry, far from giving up, is exploring new ways to enable designs to go beyond the reticle size, which is around 8... » read more

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tag: OIF

Chip Industry Week In Review

Linear Pluggable Optics Save Energy In Data Centers

Chip Industry Week In Review

AI Drives Need For Optical Interconnects In Data Centers

New Standards Push Co-Packaged Optics

1.6 Tb/s Ethernet Challenges

Many Chiplet Challenges Ahead

Waiting For Chiplet Standards

Emerging Apps And Challenges For Packaging

Designs Beyond The Reticle Limit

Trending Articles

The Sub-2nm Paradox