tag: on-chip network

When Does My SoC Design Need A NoC?
By Michael Frank - 01 Dec, 2022 - Comments: 0

By Michael Frank and Frank Schirrmeister Excluding the simplest offerings, almost every modern system-on-chip (SoC) device will implement its on-chip communications utilizing a network-on-chip (NoC). Some people question whether it is necessary to use a NoC or whether a more basic approach would suffice. What is in an SoC? An SoC is an integrated circuit (IC) that incorporates most or all ... » read more

Building Your Own NoC And The Hazards Of (Not) Changing
By Kurt Shuler - 04 Jun, 2020 - Comments: 0

There is a perennial challenge that all R&D organizations face – how much of what we develop is essential to our competitive advantage and how much can be acquired at lower cost and risk rather than built from scratch? It’s easy to believe in the heat of battle that everything we are doing must be crucial. But the world continues to change around us. What was optional yesterday may be e... » read more

On-Chip Networks Optimize Shared Memory For Multicore SoCs
By Sonics - 23 Nov, 2015 - Comments: 0

Performance of multicore SoCs is often dominated by external DRAM access, particularly in digital consumer devices running high quality video and graphics applications. Increasing core counts and newer DRAMs make the problems much more difficult. This article covers optimization of the on-chip network and memory system to achieve the required system throughput. For more information, click here. » read more

Poised For Aspect-Oriented Design?
By Brian Bailey - 13 Aug, 2015 - Comments: 8

In 1992, [getperson id=" 11046 " comment="Yoav Hollander"] had the idea to take a software programming discipline called aspect-oriented programming (AOP) and apply it to the verification of hardware. Those concepts were incorporated into the [gettech id="31021" t_name="e"] language and [getentity id="22068" e_name="Verisity"] was formed to commercialize it. Hollander had seen that using obj... » read more

Executive Insight: Grant Pierce
By Ed Sperling - 27 Jul, 2015 - Comments: 0

Grant Pierce, president and CEO of Sonics, sat down with Semiconductor Engineering to talk about the effects of industry consolidation, China's impact, and the unfolding security threat with the IoT. What follows are excerpts of that interview. SE: Consolidation is one of the big stories right now. What does that mean for your company and the industry as a whole? Pierce: It's a very inter... » read more

Tear Down The Wall Between Front-End And Back-End Teams
By Kurt Shuler - 25 Jun, 2015 - Comments: 1

As complexity of system-on-chip devices increases, it's becoming imperative for design teams and organizations to re-examine how they work with one another in order to improve productivity. One giant step in this direction is to bridge the divide between the front-end design process and the physical back-end design process. We often refer to this as a figurative “wall,” but there is real... » read more

Locking Down The Chip
By Ernest Worthman - 09 Jul, 2014 - Comments: 0

The push toward securing chips is complicated by the amount of third-party IP that is being used inside of today’s complex SoCs. This has cast new light on the potential for on-chip networks to also function in securing signals that flow through those networks. This becomes particularly important with the Internet of Things, because the source of those signals isn’t always obvious to the... » read more

Executive Insight: Grant Pierce
By Ed Sperling - 29 May, 2014 - Comments: 0

SE: What worries you most? Pierce: At the very top of my list is continuing to attract the talent into the company that we’ve managed to build up over time. Inside of Sonics, it’s a unique situation. We’re at the boundary between system-level architecture and chip-level micro-architecture for having what the system guys are looking for in the silicon. We need expertise in any IP that t... » read more

The Week In Review: Design
By Ed Sperling - 07 Mar, 2014 - Comments: 0

Tools Synopsys rolled out a new version of its software technologies for static and formal verification, which it says increases performance by up to five times. Also new are improved debug and low-power verification with native power simulation, and an integrated IP portfolio. Cadence uncorked a new version of its PCB and packaging environment, which it says speeds up timing closure by as ... » read more

Managing Memory With Embedded Software
By Ann Mutschler - 22 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler Memory is shaping up to be a key leverage point for embedded software going forward as it represents such a large fraction of the silicon real estate in today’s SoCs. Managing memory effectively and memory bandwidth also represents a significant fraction of the potential bottlenecks and the power dissipation. As such, everything embedded software can do to enhance h... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy