tag: packaging

Challenges Grow For Medical ICs
By Gregory Haley - 03 Mar, 2025 - Comments: 0

Demand for medical ICs used inside and outside the body is growing rapidly, but unique manufacturing and functional requirements coupled with low volumes have turned this into a complex and extremely challenging market. Few semiconductor applications demand this level of precision, reliability, and long-term stability. Unlike consumer electronics, where failure might mean a reboot or chip re... » read more

Energy Saving In Semiconductor Packaging Plating Processes Through Chemical Deflashing Process Optimization
By Arieff Yusoff - 20 Feb, 2025 - Comments: 0

In response to the rising focus on sustainable manufacturing practices and corporate social responsibility, there has been a surge of interest in adopting environmentally friendly and green chemicals for semiconductor manufacturing processes. These alternatives aim to minimize hazards while promoting greater sustainability. Notably, this trend extends to exploring substitutes for conventional c... » read more

An Innovative Hybrid Cleaning Approach For Contaminant Removal in Semiconductor Packaging
By Chun Yuan Lim - 23 Jan, 2025 - Comments: 0

The growing demand for power semiconductors, which control large currents and voltages, has resulted in their widespread use in various electronic devices, including electric vehicles (EVs). The requirement for greater performance and smaller devices has led to increased operating temperatures for these power semiconductors. This rise in temperature poses a challenge as it often leads to delami... » read more

Analysis Of Multi-Chiplet Package Designs And Requirements For Production Test Simplification
By Vineet Pancholi - 21 Nov, 2024 - Comments: 1

In recent years there has been a sharp rise of multi-die system designs. Numerous publications targeting a large variety of applications exist in the public domain. One presentation [2] on the IEEE’s website does a good job of detailing the anecdotal path of multi-die systems by way of chiplet building blocks integrated within a single package [2]. The presentation includes references to a ha... » read more

Revolutionizing IC Packaging With High-Density RDL Technology
By Curtis Zwenger - 24 Oct, 2024 - Comments: 0

The demand for high-performance devices, particularly in AI, HPC, and data centers, has surged dramatically in the ever-evolving landscape of integrated circuit technology. This demand has been further accelerated by the COVID-19 pandemic, pushing the boundaries of silicon technology to its limits. Enter Amkor’s S-SWIFT, a packaging solution designed to address these challenges and revolution... » read more

The Long Climb: Bringing Through Glass Vias (TGV) To High-Volume Manufacturing
By Keith Best - 15 Oct, 2024 - Comments: 0

The semiconductor industry is a land of peaks and valleys. It’s a place where each innovation represents the culmination of a long and often difficult climb to the summit. In the case of glass substrates, the peak of the mountain is in sight. The arrival of glass substrates comes at an opportune time, as the industry eyes new process innovations to meet the incredible demand for high perfo... » read more

Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications
By InRak Kim - 19 Sep, 2024 - Comments: 0

The conventional flip chip ball grid array (FCBGA) package platform has wide industry usage and provides high electrical performance. However, as high performance requirements increased, it encounters significant challenges. FCBGA packages frequently encounter underfill cracks after long term reliability or harsh reliability test conditions for automotive devices. Figure 1 shows the typical und... » read more

Simultaneous Bi-Directional Signaling: A Breakthrough Alternative For Multi-Die Assemblies
By Ramin Farjadrad - 29 Aug, 2024 - Comments: 0

In designing multi-die systems-in-package, with or without chiplets, it is easy to think of the interconnect between dies as simply analogous to the interconnect between functional blocks on a single die. But this analogy can lead architects and designers into a blind alley from which it becomes impossible to meet system performance and power requirements. The reason lies in fundamental differe... » read more

Current Characterization Of Various Cu RDL Designs In Wafer Level Packages (WLP)
By JeongMin Ju - 15 Aug, 2024 - Comments: 0

Copper (Cu) redistribution layer (RDL) technology is used to interconnect chips in various high current Wafer Level Packaging (WLP) applications. Typically, Cu RDLs with thicknesses of 5-9 µm and widths of 5-20 µm are used for high current sourcing. In this case, the temperature of the Cu RDL metal line increases due to the Joule heat generated when current passes through the metal line. If a... » read more

Five Questions To Ask When Selecting A Temporary Bonding And Debonding System
By Jessica Albright - 15 Aug, 2024 - Comments: 0

High-bandwidth memory blocks (HBM), microprocessors, field-programmable gate arrays (FPGA), AI accelerators, and other devices used in advanced system-level packaging all rely on temporary bonding and debonding systems to shrink their footprint. Understanding which properties play the most crucial role in device reliability and efficient production will ensure you are maximizing your yield, whi... » read more

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