New System Requirements Demand a Creatively Choreographed Ecosystem

By Jim Feldhan - 17 Sep, 2015 - Comments: 0

In the past, integrated circuits, packages and boards were all designed independently, and yet in most cases still managed to fit together with very few functional or technical problems. However, recent advances in chip performance have changed this process dramatically. New designs, processes and materials already have been seen in packaging as high-performance semiconductor chips need to c... » read more

Advanced IC Packaging Biz Heats Up

By Mark LaPedus - 20 Aug, 2015 - Comments: 0

After a number of false starts and lackluster adoption, the advanced IC packaging market is finally heating up. On one front, for example, a new wave of chips based on advanced [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D"] stacked-die is entering the market. And on another front, the momentum is building for new and advanced 2D packages, such as embedded package-on-package (PoP... » read more

IP Market Shifts Direction

By Ed Sperling - 03 Jun, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss intellectual property changes and challenges with Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and MSIP at [getentity id="22035" e_name="Synopsys"]; Kurt Shuler, vice president of marketing at [getentity i... » read more

What’s Different At 16/14nm?

By Ed Sperling - 28 May, 2015 - Comments: 0

Will finFETs live up to their promise? It depends on whom you ask, when you ask that question, and the intended application of a design. But across the semiconductor industry, there is general agreement that it's getting easier to work at the most advanced nodes as tools and flows are better understood and overall experience increases. There is no question that [getkc id="185" kc_name="finFE... » read more

FD-SOI Vs. FinFETs

By Ed Sperling - 30 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

Making It Differently

By Ed Sperling - 02 Apr, 2015 - Comments: 0

Anyone who hasn't bought into the IoT/E as a fundamental shift in electronics should check out what's happening in China. All appliances and electronics being developed for the home market are now being sold as smart-ready. This is a market that comprises roughly one-fifth (19.4% to be exact) of the world's population. In the future, whether or not you hook up a new washing machine or TV to ... » read more

Package Modeling Needs For A Robust IC Power Integrity Sign-Off

By Chris Ortiz - 12 Mar, 2015 - Comments: 0

Progress in IC technology has allowed chip designers to pack more functionality and continually make better use of silicon area. This trend, coupled with the need to maintain low power using techniques such as voltage islands and power and clock gating, has caused the power consumption to vary across the chip and over time. This has introduced considerable amount of transient current peaks in t... » read more

Manufacturing And Packaging Changes For 2015

By Brian Bailey - 22 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

From Specification To Chip: A Holistic Design Approach

By Kalpesh Sanghvi - 18 Dec, 2014 - Comments: 0

Chip design is getting more and more challenging in terms of power, performance, area and IP integration. At the same time, competition and time-to-market are forcing much tighter schedules. The traditional ASIC design approach taken by OEMs is to handle the majority of front-end design in-house, and then hand off either register-transfer level (RTL) code or a netlist to an outside vendor, who ... » read more

Smart Early ASIC Design Prototyping And Analysis

By Sankar Ramachandran - 04 Dec, 2014 - Comments: 0

The Power Delivery Network (PDN) is the backbone of ASIC design. It is used to supply clean power to active circuits in the IC. Voltage drop on the power rails can result in degraded performance, making delivery of noise free supply to all design elements including die, package and PCB, a challenging task. With increasing competition in the market, delivering chips on time with 'first silico... » read more

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Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: packaging