tag: panel-level fan-out

A Hybrid PLP Technology Based On A 650mm x 650mm Platform
By Eoin O'Toole - 25 Jul, 2023 - Comments: 0

A panel-level (PL) approach to fan-out (FO) packaging has been discussed for several years to reduce the cost of chip-first FO packaging based on redistribution layer (RDL) technology. More recently, multilayer high-density chip-last packages have been introduced for more advanced applications. This technology would also benefit from PL processing for cost reduction. Due to the large package di... » read more

Planning For Panel-Level Fan-out
By Mark LaPedus - 21 Nov, 2019 - Comments: 0

Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

What’s The Best Advanced Packaging Option?
By Mark LaPedus - 17 Oct, 2019 - Comments: 2

As traditional chip designs become more unwieldy and expensive at each node, many IC vendors are exploring or pursuing alternative approaches using advanced packaging. The problem is there are too many advanced packaging options on the table already, and the list continues to grow. Moreover, each option has several tradeoffs and challenges, and all of them are still relatively expensive. ... » read more

Manufacturing Bits: June 25
By Mark LaPedus - 25 Jun, 2019 - Comments: 0

Panel-level consortium Fraunhofer is moving forward with the next phase of its consortium to develop technologies for panel-level packaging. In 2016, Fraunhofer launched the original effort, dubbed the Panel Level Packaging Consortium. The consortium, which had 17 partners, developed various equipment and materials in the arena. Several test layouts were designed for process development on ... » read more

What’s Next In Advanced Packaging
By Mark LaPedus - 20 Jun, 2019 - Comments: 3

Packaging houses are readying the next wave of advanced IC packages, hoping to gain a bigger foothold in the race to develop next-generation chip designs. At a recent event, ASE, Leti/STMicroelectronics, TSMC and others described some of their new and advanced IC packaging technologies, which involve various product categories, such as 2.5D, 3D and fan-out. Some new packaging technologies ar... » read more

Manufacturing Bits: June 10
By Mark LaPedus - 10 Jun, 2019 - Comments: 1

Predicting warpage in packages At the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas, there were several papers on ways to predict variation and warpage in IC packages. Advanced packages are prone to unwanted warpage during the process flow. The warpage challenges escalate as the packages become thinner. Warpage in turn can impact yields in IC packages. ... » read more

Panel Fan-out Ramps, Challenges Remain
By Mark LaPedus - 05 Nov, 2018 - Comments: 0

After years of R&D, panel-level fan-out packaging is finally beginning to ramp up in the market, at least in limited volumes for a few vendors. However, panel-level fan-out, which is an advanced form of today’s fan-out packaging, still faces several technical and cost challenges to bring this technology into the mainstream or high-volume manufacturing. Moreover, several companies are d... » read more

Packaging Challenges For 2018
By Mark LaPedus - 08 Jan, 2018 - Comments: 0

The IC packaging market is projected to see steady growth this year, amid ongoing changes in the landscape. The outsourced semiconductor assembly and test ([getkc id="83" kc_name="OSAT"]) industry, which provides third-party packaging and test services, has been consolidating for some time. So while sales rising, the number of companies is falling. In late 2017, for example, [getentity id="2... » read more

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