tag: parallelism

Taming Concurrency
By Brian Bailey - 17 Jan, 2019 - Comments: 2

Concurrency adds complexity for which the industry lacks appropriate tools, and the problem has grown to the point where errors can creep into designs with no easy or consistent way to detect them. In the past, when chips were essentially a single pipeline, this wasn't a problem. In fact, the early pioneers of EDA created a suitable language to describe and contain the necessary concurrency ... » read more

Chip Industry In Rapid Transition
By Ed Sperling - 09 Jan, 2019 - Comments: 0

Wally Rhines, CEO Emeritus at Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about global economics, AI, the growing emphasis on customization, and the impact of security and higher abstraction levels. What follows are excerpts of that conversation. SE: Where do you see the biggest changes happening across the chip industry? Rhines: 2018 was a hot year for fab... » read more

Intel’s Next Move
By Ed Sperling - 11 Sep, 2018 - Comments: 0

Gadi Singer, vice president and general manager of Intel's Artificial Intelligence Products Group, sat down with Semiconductor Engineering to talk about Intel's vision for deep learning and why the company is looking well beyond the x86 architecture and one-chip solutions. SE: What's changing on the processor side? Singer: The biggest change is the addition of deep learning and neural ne... » read more

Bugs That Kill
By Brian Bailey - 23 Aug, 2018 - Comments: 3

Are simulation-resistant superbugs stifling innovation? That is a question Craig Shirley, president and CEO of Oski Technology, asked a collection of semiconductor executives over dinner. Semiconductor Engineering was invited to hear that discussion and to present the key points of the discussion. To promote free conversation, the participants, who are listed below, asked not to be quoted di... » read more

Why Parallelization Is So Hard
By Brian Bailey - 30 Jul, 2018 - Comments: 2

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

System enables large speedups — as much as 88-fold — on common parallel-computing algorithms (MIT)
By Technical Paper Link - 06 Jul, 2017 - Comments: 1

Source: MIT/ CSAIL: Suvinay Subramanian, Mark C. Jeffrey, Maleen Abeydeera, Hyun Ryong Lee, Victor A. Ying, Joel Emer, Daniel Sanchez As is commonly known, the chips in most modern desktop computers have four cores or processing units, which can run different computational tasks in parallel, but that the chips of the future could have dozens or even hundreds of cores, and taking advantage o... » read more

The Limits Of Parallelism
By Ann Mutschler - 22 Nov, 2016 - Comments: 0

Parallelism used to be the domain of supercomputers working on weather simulations or plutonium decay. It is now part of the architecture of most SoCs. But just how efficient, effective and widespread has parallelism really become? There is no simple answer to that question. Even for a dual-core implementation of a processor on a chip, results can vary greatly by software application, operat... » read more

Virtualization Revisited
By Ernest Worthman - 05 May, 2016 - Comments: 0

Virtual instruction set computing (VISC) is getting a second look as power and performance improvements begin to slow and [getkc id="74" comment="Moore's Law"] is supplanted by [getkc id="279" comment="Koomey's Law"]. While the current crop of [getkc id="185" kc_name="finFETs"] will likely be extended for at least one more process node, there is some debate about what comes next, whether tha... » read more

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