tag: PCIe 6.0

PCIE 6.0 Vs 5.0 — All You Need To Know
By Rambus - 09 Feb, 2022 - Comments: 0

While the PCI-SIG has announced that the release of the PCI Express® 6.0 (PCIe 6.0) specification should arrive in 2022, Rambus is already addressing the needs of early adopters looking for the most advanced PCIe 6.0 IP solutions for their SoC and ASIC designs. You can find all about the new generation specification in the article below. Click here to read more. Article or... » read more

Data Center Evolution: The Leap To 64 GT/s Signaling With PCI Express 6.0
By Rambus - 02 Feb, 2022 - Comments: 0

The PCI Express (PCIe) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard. Download this w... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Jan, 2022 - Comments: 0

Nvidia again made its case for acquiring Arm to the UK's Competition and Markets Authority (CMA). “Arm is a private for-profit business at a crossroads. After acquiring Arm several years ago, SoftBank increased Arm’s headcount, hoping to spur long-term growth in several markets, including data center and personal computer, long dominated by Intel and x86. SoftBank’s investment phase has c... » read more

Advancing Signaling Rates To 64 GT/s With PCI Express 6.0
By Tim Messegee - 13 Jan, 2022 - Comments: 0

From the introduction of PCI Express 3.0 (PCIe 3.0) in 2010 onward, each new generation of the standard has offered double the signaling rate of its predecessor. PCIe 3.0 saw a significant change to the protocol with the move from 8b/10b to highly efficient 128b/130b encoding. The PCIe 6.0 specification, now officially released, doubles the signaling rate to 64 gigatransfers per second (GT/s) a... » read more

CXL Signals A New Era Of Data Center Architecture
By Tim Messegee - 08 Jul, 2021 - Comments: 0

An exponential rise in data volume and traffic across the global internet infrastructure is motivating exploration of new architectures for the data center. Disaggregation and composability would move us beyond the classic architecture of the server as the unit of computing. By separating the functional components of compute, memory, storage and networking into pools, composed on-demand to matc... » read more

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP
By Gary Ruggles - 10 Jun, 2021 - Comments: 0

PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

PCIe 5.0 Drill-Down
By Ed Sperling - 01 Apr, 2020 - Comments: 0

Suresh Andani, senior director of product marketing for SerDes IP at Rambus, digs into the new PCI Express standard, why it’s so important for data centers, how it compares with previous versions of the standard, and how it will fit into existing and non-von Neumann architectures. » read more

Week In Review: Design, Low Power
By Jesse Allen - 21 Jun, 2019 - Comments: 0

ON Semiconductor completed its $946 million acquisition of Quantenna Communications, a San Jose-based company that specializes in Wi-Fi chips and software. Aldec introduced automatic UVM register generation to its Riviera-PRO verification platform. Riviera-PRO can now accept a CSV file or IP-XACT register description as an input and, working at the Register Abstraction Layer (RAL) of UVM, ou... » read more

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