Need For Speed Drives Targeted Testing


As packaging complexity increases and nodes shrink, defect detection becomes significantly more difficult. Engineers must contend with subtle variations introduced during fabrication and assembly without sacrificing throughput. New material stacks degrade signal-to-noise ratios, which makes metrology more difficult. At the same time, inspection systems face a more nuanced challenge — how t... » read more

Secure Handling Of Financial Data In Manufacturing


Experts at the Table: Semiconductor Engineering sat down to discuss the advantages associated with linking financial data with manufacturing data analytic platforms, real security challenges and the best uses for AI/ML methods, with Dieter Rathei, CEO of DR Yield; Jon Holt, senior director of product management at PDF Solutions, Alex Burlak, vice president of advanced analytics and test at p... » read more

2025-Product Design Enhancement With Test Structures For Non-Contact Detection Of Yield Detractors


Abstract: Detection and monitoring of the yield loss mechanisms and defects in product chips have been a subject of extensive efforts, resulting in multiple useful Design-for-Manufacturing (DFM) and Design-for-Test (DFT) techniques. Defect inspection techniques extend optical inspection further into sub-10 nm nodes, but many buried defects are formed as a result of multi-layer 3-D interaction... » read more

Improving Manufacturing Yields With Process Control Solutions


Even after 20 years or so, process control continues to be a confusing or misunderstood technology. A short description of process control is an accurate one—It’s a means of controlling manufacturing equipment and reducing variability to improve yields and performance of the products manufactured through that equipment. Tools like PDF Solutions Fault Detection and Classification (FDC)... » read more

Nearly Invisible: Defect Detection Below 5nm


Detecting sub-5nm defects creates huge challenges for chipmakers, challenges that have a direct impact on yield, reliability, and profitability. In addition to being smaller and harder to detect, defects are often hidden beneath intricate device structures and packaging schemes. Moreover, traditional optical and electrical probing methods, trusted for decades, are proving inadequate against ... » read more

Hunting For Macro Defects


Detecting macro-defects early in the wafer processing flow is vital for yield and process improvement, and it is driving innovations in both inspection techniques and wafer test map analysis. At the wafer level, a macro-defect can affect more than one die, and in some cases large regions of a wafer. Finding macro defects can indicate a significant issue with a process module, a particular fi... » read more

Accelerating Digital Transformation With Tight Integration Of Manufacturing Data


Many semiconductor companies are involved in digital transformation of their overall processes and operations. Manufacturing is one of the most critical and value generating processes in a semiconductor company. Being able to tightly integrate manufacturing with the rest of the enterprise is a critical element of a successful digital transformation program. Recognizing the value of real-time... » read more

Chip Industry Week In Review


ASML and imec signed a five-year strategic partnership to advance semiconductor innovation and sustainable technology. The collaboration will leverage ASML’s full product portfolio, including high-NA EUV, DUV immersion, and advanced metrology tools, within imec’s pilot line for sub-2nm R&D. Supported by EU and national funding, it will also drive research in silicon photonics, memory, a... » read more

Cutting IC Manufacturing Costs By Combining Data


Experts at the Table: Semiconductor Engineering sat down to discuss the benefits of incorporating financial data into fab floor decision-making, including what kind of cost data is most useful, with Dieter Rathei, CEO of DR Yield; Jon Holt, senior director of product management at PDF Solutions, Alex Burlak, vice president of advanced analytics and test at proteanTecs; and Dirk de Vries, techni... » read more

Full-Chip Voltage Contrast Inference Using Deep Learning; You Only Look Once: Voltage Contrast (YOLO-VC)


Abstract: The electron beam inspection methodology for voltage contrast (VC) defects has been widely adopted in the early stages of sub-10nm logic and memory technology development, as well as in new product introductions. However, due to throughput limitations, full-chip inspection at the 300mm wafer scale remains impractical for yield ramp and production applications. To address this challeng... » read more

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