Layout Driven Design With L-Edit Photonics


Advances in integrated circuit technology and fabrication have made it possible to leverage traditional CMOS fabrication processes and materials and apply them to the design of Photonic Integrated Circuits (PICs). The combination of PICs with traditional electronic integrated circuits, called integrated photonics, is the ability to move, modulate, and detect light on a single IC. While there is... » read more

Power/Performance Bits: Oct. 2


Photonic sensor Researchers at Washington University in St. Louis devised a way to record environmental data using a wireless photonic sensor resonator with a whispering-gallery-mode (WGM) architecture capable of resonating at light frequencies and also at vibrational or mechanical frequencies. Optical sensors are not affected by electromagnetic interference, a major benefit in noisy or har... » read more

Week In Review: Design, Low Power


Arm announced a new processor targeted at autonomous driving applications. The Cortex-A76AE is a superscalar, out-of-order processor that incorporates Split-Lock safety technology. Split-Lock allows CPU clusters in an a SoC to be configured either in ‘split mode’ for high performance, allowing two (or four) independent CPUs in the cluster to be used for diverse tasks and applications, or �... » read more

Week In Review: Design, Low Power


M&A Intel acquired NetSpeed Systems, a network-on-a-chip and interconnect fabric IP and tool provider. Founded in 2011, the San Jose-based company recently put a focus on interconnects designed with AI applications in mind. Intel has cast the acquisition as a way to tie a number of its other technologies together. The team will join Intel's Silicon Engineering Group. Intel has been a NetSp... » read more

Physical Verification For Silicon Photonics: Don’t Panic!


Silicon photonics augments traditional electrical signals in integrated circuits (ICs) with light transmission to speed up data transfer and reduce power consumption. According to MarketsandMarkets, the overall silicon photonics market is worth approximately $774.1M in 2018, and is expected to reach $1,988.2M by 2023, at a CAGR of 20.8% between 2018 and 2023  [1]. Cloud computing is one market... » read more

Week In Review: Design, Low Power


M&A Intel will acquire fabless company eASIC. Founded in 1999, eASIC sells structured ASIC platforms that act as a midpoint between FPGAs and standard cell ASICs by combining FPGA-like logic and design flows with single via routing. Eventually, Intel sees potential in using its Embedded Multi-Die Interconnect Bridge (EMIB) technology to combine Intel FPGAs with structured ASICs in a system... » read more

Power/Performance Bits: May 29


Using bandwidth like a fish Researchers from the University of Georgia developed a method to make fuller use of wireless bandwidth, inspired by a cave-dwelling fish's jamming avoidance response. Eigenmannia fish live in complete darkness, sensing their environment and communicating through emitting an electric field. When two fish emit signals at similar frequencies they can interfere with ... » read more

The Week In Review: Design


Tools Synopsys debuted new versions of its circuit simulation and custom design products. FineSim SPICE provides 2X faster simulation and Monte Carlo analysis speed, CustomSim FastSPICE offers 2X speed-up for post-layout SRAM simulation and maintains multi-core scalability by providing additional 2X speed-up on four cores, and HSPICE delivers 1.5X speed-up for large post-layout designs, accord... » read more

Silicon’s Long Game


The era of all-silicon substrates and copper wires may be coming to an end. Progress in the future increasingly depends on more exotic combinations of materials that are developed for specific applications. But after years of predicting the death of silicon, it appears those predictions may be premature. That's not always obvious, given the growing number of chemical combinations being creat... » read more

Fan-Outs vs. TSVs


Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

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