tag: PLL

Research Bits: July 24
By Jesse Allen - 24 Jul, 2023 - Comments: 0

Protons improve ferroelectric memory Researchers from King Abdullah University of Science and Technology (KAUST), Qingdao University, and Zhejiang University developed a method to produce multiple phase transitions in ferroelectric materials, which could increase storage capacity for neuromorphic memory. The approach uses proton-mediation of the ferroelectric material indium selenide. The r... » read more

Research Bits: Feb. 21
By Susan Rambo - 21 Feb, 2023 - Comments: 0

High-quality ‘chirps’ for automotive, industrial mmWave radar Imec demonstrated a low-power phase-locked loop (PLL) that generates high-quality frequency-modulated continuous-wave (FMCW) signals for mmWave radar, which can be used in short-range automotive and industrial radar applications. The FMCW radars popular in healthcare, automotive, and industrial send out sinusoidal waves that get... » read more

All-Digital MDL-Based Fast Lock Clock Generator For Low-Power Chiplet-Based SoC Design
By Technical Paper Link - 14 Dec, 2022 - Comments: 0

A new technical paper titled "A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems" was published by researchers at Hongik University, Seoul, South Korea. "An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digi... » read more

High-Speed Signaling Drill-Down
By Bryon Moyer - 17 Jun, 2020 - Comments: 0

Chip interconnect standards have received a lot of attention lately, with parallel versions proliferating for chiplets and serial versions moving to higher speeds. The lowliest characteristic of these interconnect schemes is the physical signaling format. Having been static at NRZ (non-return-to-zero) for decades, change is underway. “Multiple approaches are likely to emerge,” said Brig ... » read more

Choosing Power-Saving Techniques
By Ann Mutschler - 16 Jan, 2017 - Comments: 1

Engineers have come up with a long list of ways to save power in chip and system designs, but there are few rules to determine which approaches work best for any given design. There is widespread confusion about what techniques should be used where, which IP or subsystem is best, and how everything should be packaged together. The choices include everything from the proper level of clock and... » read more

DVFS On The Sidelines
By Brian Bailey - 13 Aug, 2015 - Comments: 2

Power reduction is one of the most important aspects of chip design these days, but not all power reduction techniques are used equally. Some that were once important are fading and dynamic voltage, and frequency scaling (DVFS) is one of them. What's changed, and will we see a resurgence in the future? What is it? DVFS has physics powerfully in its favor. As Vinod Viswanath, director of res... » read more

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