Design Tool Think Tank Required

By Brian Bailey - 29 Feb, 2024 - Comments: 1

When I was in the EDA industry as a technologist, there were three main parts to my role. The first was to tell customers about new technologies being developed and tool extensions that would be appearing in the next release. These were features they might find beneficial both in the projects they were undertaking today, and even more so, would apply to future projects. Second, I would try and ... » read more

Searching For Power Bugs

By Brian Bailey - 15 Oct, 2020 - Comments: 0

How much power is your design meant to consume while performing a particular function? For many designs, getting this right may separate success from failure, but knowing that right number is not as easy as it sounds. Significant gaps remain between what power analysis may predict and what silicon consumes. As fast as known gaps are closed, new challenges and demands are being placed on the ... » read more

Raising The Abstraction Level For Power

By Brian Bailey - 09 May, 2019 - Comments: 0

Power-aware design is still a relatively new concern for many semiconductor products, and since inception it has changed several times and in different ways. Initially people were concerned about peak power. Today, they care about peak, total energy, thermal and other effects. The industry has tried several abstractions ranging from system-level analysis, which promised to swamp implementati... » read more

Power Just One Piece Of The Puzzle At 10nm And Below

By Ann Mutschler - 11 May, 2017 - Comments: 0

With dynamic power density and rising leakage power becoming more problematic at each new node, it is more important than ever to look at designs today with power in mind from the very start. As part of this complex picture of electronic design today, every piece in the design flow must tie together for the greatest efficiency and optimization. While this is partly power, there are more... » read more

Time To Pay The Piper

By Brian Bailey - 28 Jul, 2016 - Comments: 3

The Pied Piper of Hamelin is a German fable about a rat catcher who used his magic pipe to lure away rats. When he was not paid by the town, he used his pipe to lure away all of the town's children. I am not suggesting that exactly the same is true for the semiconductor industry and having not paid [getkc id="7" kc_name="EDA"], but I do not think they have paid enough and they will now have to ... » read more

Powerful New Standard

By Brian Bailey - 02 Mar, 2016 - Comments: 1

In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

Trouble Ahead For IP industry?

By Brian Bailey - 14 May, 2015 - Comments: 0

[getkc id="106" kc_name="Power-aware design"] has risen from an afterthought to a primary design constraint for some design types. Initially it was smart phones and other battery operated devices. It has consistently expanded into additional areas including those plugged into the wall and those plugged into the grid. Some parts of the world are imposing restrictions on the power that a device c... » read more

Industry Collaboration Starts

By Jesse Allen - 07 Nov, 2014 - Comments: 0

Last week was quite exciting for the Knowledge Center. We have started to receive our first vendor supplied pages along with obtaining permission to mine various documents for populating other pages. A big thank you for these early contributions. Several people also sent in photographs for inclusion on their personal pages as well as additional information or corrections. It all started whe... » read more

Google Project Ara And The Low-Power Imperative

By Brian Fuller - 08 May, 2014 - Comments: 2

You’ve no doubt seen the slides: 50 billion Internet of Things (IoT) devices by 2020. That’s an amazing number, but consider this: What if they each draw 1W? All things begin equal, we’d have to build another 50 nuclear power plants in the world to handle that additional energy requirement. (Something tells me that outcome is unrealistic). Power takes center stage as we evolve into ... » read more

Combining Power And Synthesis

By Ann Mutschler - 14 Jan, 2010 - Comments: 0

By Ann Steffora Mutschler Each passing design node shrinks electronic designs ever smaller and more complex, which has made power management a critical design priority – even in the synthesis step in the design flow. Synthesis has always been an integral part of the design process, particularly at the RTL level. But as chip design has become more complicated, the need to raise the pro... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?