System-Aware SoC Power, Noise And Reliability Sign-off


In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

Power Noise And Reliability Sign-off For The Sub-20nm FinFET Era


There is a greater focus on power noise and reliability simulations and sign-off as the complexity of SoC designs continue to increase with 100+ different voltage islands, clock and power gating techniques, and multiple IPs each operating on different clock and power domains, etc. The technology node migration from 40nm to 20nm is driving requirements for electro-migration (EM) and reliability ... » read more

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