tag: PPA

Optimizing Power And Performance For Machine Learning At The Edge
By Mike Fingeroff - 12 Dec, 2019 - Comments: 0

While machine learning (ML) algorithms are popular for running on enterprise Cloud systems for training neural networks, AI/ML chipsets for edge devices are growing at a triple digit rate, according to Tractica “Deep Learning Chipsets” (Figure 1). Edge devices include automobiles, drones, and mobile devices that are all employing AI/ML to provide valuable functionality. Figure 1: Marke... » read more

Rapid Evolution For Verification Plans
By Brian Bailey - 28 Oct, 2019 - Comments: 0

Verification plans are rapidly evolving from mechanisms to track verification progress into multi-faceted coordination vehicles for several teams with disparate goals, using complex resource management spread across multiple abstractions and tools. New system demands from industries such as automotive are forcing tighter integration of those plans with requirements management and product lif... » read more

Disaggregation Of The SoC
By Ed Sperling - 24 Oct, 2019 - Comments: 0

The rise of edge computing could do to the cloud what the PC did to the minicomputer and the mainframe. In the end, all of those co-existed (despite the fact that the minicomputer morphed into commodity servers from companies like Dell and HP). What's different this time around is that the computing done inside of those boxes is moving. It is being distributed in ways never considered feasi... » read more

Multiphysics Simulations for AI Silicon to System Success
By Ansys - 09 Oct, 2019 - Comments: 0

Achieving power efficiency, power integrity, signal integrity, thermal integrity and reliability is paramount for enabling product success by overcoming the challenges of size and complexity in AI hardware and optimizing the same for rapidly evolving AI software. ANSYS’ comprehensive chip, package and system solutions empower AI hardware designers by breaking down design margins and siloed de... » read more

In-Chip Monitoring Becoming Essential Below 10nm
By Ann Mutschler - 20 May, 2019 - Comments: 0

Rising systemic complexity and more potential interactions in heterogeneous designs is making it much more difficult to ensure a chip, or even a block within a chip, will functioning properly without actually monitoring that behavior in real-time. Continuous and sporadic monitoring have been creeping into designs for the past couple of decades. But it hasn’t always been clear how effective... » read more

Low Power Meets Variability At 7/5nm
By Ann Mutschler - 11 Apr, 2019 - Comments: 0

Power-related issues are beginning to clash with process variation at 7/5nm, making timing closure more difficult and resulting in re-spins caused by unexpected errors and poor functional yield. Variability is becoming particularly troublesome at advanced nodes, and there are multiple causes of that variability. One of the key ones is the manufacturing process, which can be affected by every... » read more

Reliability Becomes The Top Concern In Automotive
By SE Staff - 12 Feb, 2019 - Comments: 4

Reliability is emerging as the top priority across the hottest growth markets for semiconductors, including automotive, industrial and cloud-based computing. But instead of replacing chips every two to four years, some of those devices are expected to survive for up to 20 years, even with higher usage in sometimes extreme environmental conditions. This shift in priorities has broad ramificat... » read more

Data Vs. Physics
By Ed Sperling - 10 Jan, 2019 - Comments: 0

The surge of data from nearly ubiquitous arrays of sensors is changing the dynamics of where and how that data is processed. There is simply too much data to send everything to a centralized processing facility in the cloud, and even 5G won't provide enough bandwidth to handle all of this data. This has big implications on a much broader scale. Data is valuable. And while clean data is more ... » read more

Where ML Works Best
By Ed Sperling - 26 Jul, 2018 - Comments: 0

Anirudh Devgan, president of Cadence, sat down with Semiconductor Engineering to discuss machine learning inside and outside of EDA tools and how that will affect the future of chip and system design. What follows are excerpts of that discussion. SE: How do you see the market and use of machine learning shaping up? Devgan: There are three main areas—machine learning inside, machine lear... » read more

Safety, Security And PPA Tradeoffs
By Brian Bailey - 23 Jul, 2018 - Comments: 0

Safety and security are emerging as key design tradeoffs as chips are added into safety-critical markets, adding even more complexity into an already complicated optimization process. In the early days of semiconductor design, performance and area were traded off against each other. Then power became important, and the main tradeoffs became power, performance and area (PPA). But as chips inc... » read more

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