Nanosheet GAAFETs: Compact Modeling (Politecnico di Torino)


A technical paper titled “NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance” was published by researchers at Politecnico di Torino. Abstract: "NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as ... » read more

Dealing With Sub-Threshold Variation


Chipmakers are pushing into sub-threshold operation in an effort to prolong battery life and reduce energy costs, adding a whole new set of challenges for design teams. While process and environmental variation long have been concerns for advanced silicon process nodes, most designs operate in the standard “super-threshold” regime. Sub-threshold designs, in contrast, have unique variatio... » read more

Accuracy In Optical Overlay Metrology


By Barak Bringoltz, Tal Marciano, Tal Yaziv, Yaron DeLeeuw, Dana Klein, Yoel Feler, Ido Adam, Evgeni Gurevich, Noga Sella, Ze’ev Lindenfeld, Tom Leviant, Lilach Saltoun, Eltsafon Ashwal, Dror Alumot and Yuval Lamhot, Xindong Gao, James Manka, Bryan Chen, and Mark Wagner. Abstract In this paper we discuss the mechanism by which process variations determine the overlay accuracy of optical m... » read more