Rethinking Chip Economics

By Ed Sperling - 20 Mar, 2024 - Comments: 0

As process nodes shrink, so does the selection of chips developed at those nodes. Consumers demand more features and functionality, but that carries a high price tag in terms of both complexity and real dollars. In addition, because costs are skyrocketing, there is growing pressure for those chips to remain reliable and up-to-date for longer periods of time. Jayson Bethurem, vice president of m... » read more

Massive IoT Interop Fuels Protocol Battle

By Bryon Moyer - 15 Jul, 2021 - Comments: 0

Wireless standards are plentiful, but most are not capable of being scaled to the level of a smart city. As a result, such networks have been built application-by-application using proprietary stacks, often with non-interoperable network layers. That, in turn, has slowed the proliferation of dense wireless connectivity at scale. “In a hyper-connected world, connectivity choices are driv... » read more

Battle Brewing Over Automotive Display Protocols

By Bryon Moyer - 06 May, 2021 - Comments: 0

Displays are multiplying in new and future automobiles. That means a lot more display data moving around the vehicle and traveling some distance between sensor and processor. While existing protocols can handle some of the new duties, new protocols also are being developed specifically for this application. “Automotive displays are proliferating, increasing in numbers and in pixel densi... » read more

Heterogeneous Cache Coherence Requires A Common Internal Protocol

By Kurt Shuler - 30 Nov, 2017 - Comments: 0

Machine learning and artificial intelligence systems are driving the need for systems-on-chip containing tens or even hundreds of heterogeneous processing cores. As these systems expand in size and complexity, it becomes too difficult to manage data flow solely through software means. An approach that simplifies software while improving performance and power consumption is to implement hardware... » read more

Performance Increasingly Tied To I/O

By Ed Sperling - 18 Jan, 2017 - Comments: 0

Speeding up input and output is becoming a cornerstone for improving performance and lowering power in SoCs and ASICs, particularly as scaling processors and adding more cores produce diminishing returns. While processors of all types continue to improve, the rate of improvement is slowing at each new node. Obtaining the expected 30% to 50% boost in performance and lower power no longer can ... » read more

Executive Insight: K. Charles Janac

By Ed Sperling - 24 May, 2016 - Comments: 0

K. Charles Janac, chairman and CEO of Arteris, sat down with Semiconductor Engineering to talk about what's changing in the automotive market, the impact of big data, and heterogeneous cache coherency. What follows are excerpts of that discussion. SE: What are the big changes you're seeing in semiconductor design? Janac: There are a lot of changes right now. Mobility is slowing down and b... » read more

Power, Standards And The IoT

By Ed Sperling - 15 Oct, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power, standards and the IoT with Jerry Frenkil, director of open standards at [getentity id="22055" comment="Si2"]; Frank Schirrmeister, group director of product marketing of the System Development Suite at [getentity id="22032" e_name="Cadence"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"]; and Vojin Zivojno... » read more

A Primer For The 802.XX Physical Layer

By Ernest Worthman - 07 Oct, 2015 - Comments: 0

This is the second installment of the 802.XX for the IoE series of articles. The first one was published in the August issue and addressed the Media Access Control (MAC) layer. In this article, we will examine the elements of the physical (PHY) layer of the 802.11 protocol stack. For reference, the protocol stack is shown in figure 1. The best designs, like everything else, are built on a so... » read more

Tech Talk: SoC Protocol Debug

By Ed Sperling - 24 Sep, 2015 - Comments: 0

Bernie DeLay, group director for verification IP R&D at Synopsys, talks about what goes wrong in complex SoCs, how so-called standard pieces play together, and where are the gotchas in re-use. [youtube vid=AaY_AmdjUpo] » read more

802.XX And The IoE

By Ernest Worthman - 03 Sep, 2015 - Comments: 0

Ever since the first 802.11 standard was published in 1997, it has evolved to become the de facto protocol for much of the wireless networking across a wide range of devices and implementations. Today the protocol family includes 802.b 802.11a, 802.11g, 802.11n, and 802.11ac, respectively. Some of these will play a very important role in the IoE. There are other 802.xx protocols (such as 802.15... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: protocols