FIR And Median Filter Accelerators In CodAL

By Codasip - 25 Oct, 2023 - Comments: 0

5G is the latest generation of cellular networks using the 3rd Generation Partnership Project (3GPP) 5G New Radio air interface. Unlike previous generations of network (2G, 3G & 4G) which had a one-size-fits-all approach, 5G aims to address a wide range of very different applications. To flexibly support diverse quality of service requirements, network slicing is introduced to enable mul... » read more

Edge Computing: Four Smart Strategies For Safeguarding Security And User Experience

By Keysight - 21 Jun, 2023 - Comments: 0

It is a brave new world for enterprise networks. Smart devices are getting smarter, and edge computing is emerging as a viable way to reduce latency and improve performance. But as network architectures grow increasingly amorphous, what kind of impact will this have on security and performance? Download this white paper to discover how you can boost security, ensure quality of service, and futu... » read more

Zen And The Art Of Network Timestamping

By Marvell - 28 Feb, 2018 - Comments: 0

Network devices, namely switches and routers, are used for forwarding data packets from their source to their destination - or at least that is what they are meant to do. In practice, these devices tend to do a lot more than that. They can be involved in Quality of Service (QoS) enforcement, filtering, load balancing, fault detection, performance measurement, event logging and various other act... » read more

Optimizing DDR Memory Subsystem Efficiency

By Synopsys - 24 Feb, 2016 - Comments: 0

The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its performance requirements and a system that delivers poor performance, or even fails to operate correctly. State-of-the-art DDR memory controllers use advanced arbitration and scheduling policies to optimize DDR memory efficiency. At the same time, t... » read more

An Architecture Synthesis Platform For Rapidly Evolving SoC Designs

By NetSpeed Systems - 24 Feb, 2016 - Comments: 0

Modern System-on-Chip (SoC) architects are faced with a number of serious challenges. First, the number of Semiconductor Intellectual Property (IP) blocks in SoC designs is growing continuously and increasing design complexity. With IP design reuse becoming more common, the mixing and matching of IP components is further compounding design complexity. Second, sophisticated SoC applications are ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: quality of service

FIR And Median Filter Accelerators In CodAL

Edge Computing: Four Smart Strategies For Safeguarding Security And User Experience

Zen And The Art Of Network Timestamping

Optimizing DDR Memory Subsystem Efficiency

An Architecture Synthesis Platform For Rapidly Evolving SoC Designs