The Chip Industry’s Next-Gen Roadmap

By Mark LaPedus - 21 Jan, 2021 - Comments: 1

Todd Younkin, the new president and chief executive of the Semiconductor Research Corp. (SRC), sat down with Semiconductor Engineering to talk about engineering careers, R&D trends and what’s ahead for chip technologies over the next decade. What follows are excerpts of that conversation. SE: As a U.S.-based chip consortium, what is SRC's charter? Younkin: The Semiconductor Research... » read more

Speeding Up The R&D Metrology Process

By Mark LaPedus - 16 Jul, 2020 - Comments: 0

Several chipmakers are making some major changes in the characterization/metrology lab, adding more fab-like processes in this group to help speed up chip development times. The characterization/metrology lab, which is generally under the radar, is a group that works with the R&D organization and the fab. The characterization lab is involved in the early analytical work for next-generati... » read more

Key Drivers In New Chip Industry Outlook

By Ed Sperling - 04 May, 2020 - Comments: 0

How well the semiconductor industry fares over the next 12 to 24 months depends upon the evolution of a virus. That alone will determine the correct model for an economic rebound — V, U, extended U, or maybe even a double U. But what's also becoming clear is those models don't apply uniformly to all sectors or sub-sectors of the semiconductor industry. Looked at as a whole, the entire indu... » read more

MEMS And Sensor Tech For The Next Decade

By Maria Vetrano - 17 Oct, 2019 - Comments: 0

Most of today’s blockbuster MEMS products – from pressure sensors and resonators to accelerometers and microphones – originated from academic research, a trend that Alissa M. Fitzgerald, Founder & Managing Member, A.M. Fitzgerald & Associates, expects to continue. While many of these potentially game-changing new technologies will require many more years of intensive development a... » read more

A Different Foundry Model

By Joanne Itow - 17 Oct, 2019 - Comments: 0

As the pursuit to produce advanced semiconductors that keep up with the Moore’s Law treadmill becomes more and more challenging, many companies are seeking other ways to provide the next ‘must-have’ electronic products. In fact, many companies have realized that the need for doubling performance is no longer the main attribute necessary to deliver successful solutions for IoT, automotive,... » read more

Multiple Approaches To Memory Challenges

By Ryan Gibson - 21 Feb, 2019 - Comments: 0

As we enter the era of Big Data and Artificial Intelligence (AI), it is amazing to think about the possibilities for a truly seismic shift in the changing requirements for memory solutions. The massive amount of data humans generate every year is astounding and yet is expected to increase five-fold in the next few years from machine-generated data. Further compounding this growth is the emergin... » read more

Cryogenic Etch Re-Emerges

By Mark LaPedus - 20 Sep, 2018 - Comments: 0

After years in R&D, a technology called cryogenic etch is re-emerging as a possible option for production as the industry faces new challenges in memory and logic. Cryogenic etch removes materials in devices with high aspect ratios at cold temperatures, although it has always been a challenging process. Cryogenic etch is difficult to control and it requires specialized cryogenic gases in... » read more

Leti’s Next Focus

By Mark LaPedus - 19 Jul, 2018 - Comments: 0

Emmanuel Sabonnadière, chief executive of Leti, sat down with Semiconductor Engineering to discuss R&D trends, a new deal with Soitec, and the latest developments at the France-based research organization. Leti is a research institute of CEA Tech. What follows are excerpts of that conversation. SE: Leti recently formed an alliance with Soitec. Under the terms, Leti and Soitec are formin... » read more

What’s Next In R&D?

By Mark LaPedus - 21 Jun, 2018 - Comments: 1

Luc Van den hove, president and chief executive of Imec, sat down with Semiconductor Engineering to discuss R&D challenges and what’s next in the arena. The Belgium R&D organization is working on AI, DNA storage, EUV, semiconductors and other technologies. What follows are excerpts of that conversation. SE: Moore’s Law is slowing down. And it is becoming more expensive to move fr... » read more

Europe’s New R&D Program

By Emir Demircan - 15 Feb, 2018 - Comments: 0

European Union (EU) research, development and innovation programs have proved successful in recent decades. The current framework program (FP) Horizon 2020, with its 80 billion EUR total budget – around 17 billion EUR of which is allocated for Industrial Leadership – has produced unparalleled collaboration opportunities that no single European country can match on its own. FPs are strate... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?