tag: RC delay

LP Verification
By Ed Sperling - 08 Mar, 2013 - Comments: 0

Functional verification has been a consideration throughout the design flow for the past several process nodes. Low power verification has been more of an afterthought. That’s beginning to change, though, as the challenge of integrating IP blocks and the physical effects of shrinking wires and RC delays in interconnects begin affecting power and performance in designs. What’s becoming cl... » read more

Interconnect Troubles
By Applied Materials Writers - 13 Dec, 2012 - Comments: 0

By Mehul Naik These days, transistor scaling is driving some of the most exciting innovations in device architecture and getting lots of attention as a result. What may be less obvious is the cascading effect transistor scaling is having on the interconnect. The biggest challenges result directly from pitch reduction required to support the increasing functionality. These include poor pattern ... » read more

The Return Of RC Delay
By Ed Sperling - 14 Nov, 2012 - Comments: 0

Semiconductor Manufacturing & Design talks with Mehul Naik of Applied Materials about why RC delay has become a hot topic again, and what will be necessary to solve it. [youtube vid=aQjqcpZWi0A] » read more

Deep Inside Intel
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Mark Bohr, senior fellow at Intel, to talk about a wide range of manufacturing and design issues Intel is wrestling with at advanced nodes—and just how far the road map now extends. SMD: Will EUV make 10nm? And if it doesn’t, what effect will that have on Intel? Bohr: For a process module as critical as lithography... » read more

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