Interconnect Troubles

Shrinking transistors is affecting pattern integrity and reliability, and increasing RC delay. What can be done about it?


By Mehul Naik
These days, transistor scaling is driving some of the most exciting innovations in device architecture and getting lots of attention as a result. What may be less obvious is the cascading effect transistor scaling is having on the interconnect. The biggest challenges result directly from pitch reduction required to support the increasing functionality. These include poor pattern integrity, increased RC delay, and inferior reliability.

Pattern integrity always has been important, but never to the degree that we face now. Already, the industry has moved to hard mask-based process flows for compatibility with double patterning at and below the 2x nm node. TiN is the most commonly used. Its high selectivity during low-k etch is an advantage, but the high compressive stress of these masks combined with the low mechanical strength of ultra-low-k (ULK) materials can cause buckling of interconnect lines. Lowering TiN hard mask stress is the logical solution to relieve line buckling.

Unfortunately, it is not as simple as that. Lowering the stress in conventionally deposited TiN reduces the density of the film and that leads to poor dielectric etch selectivity. We need to create a lower-stress TiN without affecting the density. The solution lies in advanced PVD technology that generates greater plasma density that makes possible low-energy deposition with less bombardment. In this way, a high-density, low-stress hard mask can be created with all the attendant benefits of no buckling, high selectivity, and scalability.

As for RC delay, the 14nm node is likely to be the inflection point beyond which copper resistivity increases exponentially. The reason lies in greater scattering at sidewalls, surfaces in copper lines with diameters less than 40nm. Just imagine what the effect will be at the 14nm node, where metal line widths will shrink to as little as 22nm.

Maximizing copper volume and grain size while minimizing scattering will be key in keeping resistance in check. Thickness of high resistance barrier-liner layers together with interfacial effects, have an increased contribution to the overall resistance of the line.

All things being equal, up to 35% lower resistance can be achieved by thinning liners from 3nm to 1nm. Recently developed copper reflow techniques can produce a larger grain size, but the scattering issue is going to require more disruptive and high-risk approaches. One possibility is a dielectric-copper interface. For this to be viable though, a new materials system will be required, such as self-forming barriers. And, new fill techniques will be needed that do not require a conducting substrate.

Advanced patterning has substantially raised the reliability stakes. While self-aligned double patterning can be used to avoid line-to-line overlay issues, via patterning still requires litho-etch-litho-etch. Line-via shorting and TDDB will become key limiters. These means that self-aligned via (SAV) schemes will be required. But although SAV may resolve line-via overlay issues at the same level, level-to-level alignment scaling is going to remain a serious challenge. Interfaces and bulk low-κ materials will have to be dramatically improved to satisfy TDDB requirements for the ≤10nm node.

Shortened electromigration (EM) lifetimes are another challenge. In this case, CVD-based selective metal capping has yielded encouraging results in preventing diffusion at the copper-dielectric barrier interface; studies show up to 80X improvement in EM. This is a scalable solution as the metal does not require aggressive pre- or post-cleaning; does not increase resistivity by diffusing into the copper; and is ≤2.5nm thick, which minimizes the impact on capacitance.

—Mehul Naik is a distinguished member of the technical staff at Applied Materials.

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