Easy-To-Use Reliability Checks Throughout The Design Cycle From IP To Full-Chip Tapeout

By Hossam Sarhan - 27 Apr, 2023 - Comments: 0

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification is no longer practical for design teams. There is a constant push to shift targeted verification activities “left” to earlier stages in the design flow. Finding and eliminating selected errors earlier during design and implementation, wh... » read more

2.5/3D IC Reliability Verification Has Come A Long Way

By Dina Medhat - 01 Aug, 2022 - Comments: 0

2.5D/3D integrated circuits (ICs) have evolved into an innovative solution for many IC design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the ... » read more

Challenges In RF Design

By Roland Jancke - 14 Oct, 2021 - Comments: 0

Designing highly integrated components for radio frequency applications poses special challenges for system engineers, designers and the commissioning engineers. The boundary between chip, package and board is increasingly vanishing on modern components. It is growing more common for parts of the functionality to be moved to the package or even the board. In some cases, the requirements have be... » read more

ESD P2P And CD Verification Doesn’t Have To Be Hard

By Abdellah Bakhali - 24 Nov, 2020 - Comments: 0

As a designer or verification engineer, you’re fighting the effects of electrostatic discharge (ESD) in your integrated circuit (IC) designs all the time. ESD is one of those frustrating issues that can challenge even the most experienced designers. Once an IC is in the market, unexpected electrical shorts will cause immediate failure or dielectric breakdown will result in gradual circuit deg... » read more

Knowledge Centers
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tag: reliability verification

Easy-To-Use Reliability Checks Throughout The Design Cycle From IP To Full-Chip Tapeout

2.5/3D IC Reliability Verification Has Come A Long Way

Challenges In RF Design

ESD P2P And CD Verification Doesn’t Have To Be Hard