Easy-To-Use Reliability Checks Throughout The Design Cycle From IP To Full-Chip Tapeout

By Hossam Sarhan - 27 Apr, 2023 - Comments: 0

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification is no longer practical for design teams. There is a constant push to shift targeted verification activities “left” to earlier stages in the design flow. Finding and eliminating selected errors earlier during design and implementation, wh... » read more

2.5/3D IC Reliability Verification Has Come A Long Way

By Dina Medhat - 01 Aug, 2022 - Comments: 0

2.5D/3D integrated circuits (ICs) have evolved into an innovative solution for many IC design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the ... » read more

Challenges In RF Design

By Roland Jancke - 14 Oct, 2021 - Comments: 0

Designing highly integrated components for radio frequency applications poses special challenges for system engineers, designers and the commissioning engineers. The boundary between chip, package and board is increasingly vanishing on modern components. It is growing more common for parts of the functionality to be moved to the package or even the board. In some cases, the requirements have be... » read more

ESD P2P And CD Verification Doesn’t Have To Be Hard

By Abdellah Bakhali - 24 Nov, 2020 - Comments: 0

As a designer or verification engineer, you’re fighting the effects of electrostatic discharge (ESD) in your integrated circuit (IC) designs all the time. ESD is one of those frustrating issues that can challenge even the most experienced designers. Once an IC is in the market, unexpected electrical shorts will cause immediate failure or dielectric breakdown will result in gradual circuit deg... » read more

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: reliability verification

Easy-To-Use Reliability Checks Throughout The Design Cycle From IP To Full-Chip Tapeout

2.5/3D IC Reliability Verification Has Come A Long Way

Challenges In RF Design

ESD P2P And CD Verification Doesn’t Have To Be Hard

Trending Articles

Hybrid Bonding Makes Strides Toward Manufacturability

Americas Chip Funding Energizes Industry

Advanced Packaging Driving New Collaboration Across Supply Chain

Startup Funding: Q3 2024

Chiplets Make Progress Using Interconnects As Glue

Knowledge Centers
Entities, people and technologies explored