tag: ReRAM

Main Applications And Corresponding Requirements For IMC With RRAM Devices
By Technical Paper Link - 06 May, 2025 - Comments: 0

A new technical paper titled "Resistive Switching Random-Access Memory (RRAM): Applications and Requirements for Memory and Computing" was published by researchers at Politecnico di Milano, IUNET and Hewlett-Packard Labs. Abstract "In the information age, novel hardware solutions are urgently needed to efficiently store and process increasing amounts of data. In this scenario, memory device... » read more

ReRAM-Based, In-Memory Implementation Of Stochastic Computing
By Technical Paper Link - 14 Apr, 2025 - Comments: 0

A new technical paper titled "All-in-Memory Stochastic Computing using ReRAM" was published by researchers at TU Dresden, Center for Scalable Data Analytics and Artificial Intelligence (ScaDS.AI), Case Western Reserve University, University of Louisiana at Lafayette and Barkhausen Institut. Abstract "As the demand for efficient, low-power computing in embedded and edge devices grows, tradit... » read more

HW Implementation Of An ONN Coupled By A ReRAM Crossbar Array (IBM, TU Eindhoven)
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "Hardware Implementation of Ring Oscillator Networks Coupled by BEOL Integrated ReRAM for Associative Memory Tasks" was published by researchers at IBM Research Europe and Eindhoven University of Technology. Abstract "We demonstrate the first hardware implementation of an oscillatory neural network (ONN) utilizing resistive memory (ReRAM) for coupling elements. ... » read more

Design Space For The Device-Circuit Codesign Of NVM-Based CIM Accelerators (TSMC)
By Technical Paper Link - 24 Feb, 2025 - Comments: 0

A new technical paper titled "Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators" was published by TSMC researchers. Abstract "Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devices. Nonvolatile memory (NVM) devices offer one s... » read more

Power Delivery Challenges in 3D HI CIM Architectures for AI Accelerators (Georgia Tech)
By Technical Paper Link - 07 Feb, 2025 - Comments: 0

A new technical paper titled "Co-Optimization of Power Delivery Network Design for 3D Heterogeneous Integration of RRAM-based Compute In-Memory Accelerators" was published by researchers at Georgia Tech. Abstract: "3D heterogeneous integration (3D HI) offers promising solutions for incorporating substantial embedded memory into cutting-edge analog compute-in-memory (CIM) AI accelerators, ad... » read more

Non-Stateful Logic Gates in ReRAM (RWTH Aachen, FZJ)
By Technical Paper Link - 08 Nov, 2024 - Comments: 0

A new technical paper titled "Experimental Verification and Evaluation of Non-Stateful Logic Gates in Resistive RAM" was published by researchers at RWTH Aachen University and Forschungszentrum Jülich GmbH (FZJ). Abstract "Resistively switching, non-volatile memory devices facilitate new logic paradigms by combining storage and processing elements. Several non-stateful concepts such as Sco... » read more

Research Bits: Sept. 24
By Jesse Allen - 24 Sep, 2024 - Comments: 0

Modeling negative capacitance Researchers from Lawrence Berkeley National Laboratory developed an open-source 3D simulation framework capable of modeling the atomistic origins of negative capacitance in ferroelectric thin films at the device level. When a material has negative capacitance, it can store a greater amount of electrical charge at lower voltages. The team believes the FerroX fra... » read more

NeuroHammer Attacks on ReRAM-Based Memories
By Technical Paper Link - 21 Jun, 2024 - Comments: 0

A new technical paper titled "NVM-Flip: Non-Volatile-Memory BitFlips on the System Level" was published by researchers at Ruhr-University Bochum, University of Duisburg-Essen, and Robert Bosch. Abstract "Emerging non-volatile memories (NVMs) are promising candidates to substitute conventional memories due to their low access latency, high integration density, and non-volatility. These super... » read more

Memory On Logic: The Good And Bad
By Brian Bailey - 11 Apr, 2024 - Comments: 0

The chip industry is progressing rapidly toward 3D-ICs, but a simpler step has been shown to provide gains equivalent to a whole node advancement — extracting distributed memories and placing them on top of logic. Memory on logic significantly reduces the distance between logic and directly associated memory. This can increase performance by 22% and reduce power by 36%, according to one re... » read more

Building CFETs With Monolithic And Sequential 3D
By Katherine Derbyshire - 22 Feb, 2024 - Comments: 0

Successive versions of vertical transistors are emerging as the likely successor to finFETs, combining lower leakage with significant area reduction. A stacked nanosheet transistor, introduced at N3, uses multiple channel layers to maintain the overall channel length and necessary drive current while continuing to reduce the standard cell footprint. The follow-on technology, the CFET, pushes... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy