The Threat Of Supply Chain Insecurity

By Ann Mutschler - 07 Sep, 2023 - Comments: 3

Concerns about counterfeit chips are growing as more chips are deployed in safety- and mission-critical applications, prompting better traceability and new and inexpensive solutions that can determine if chips are new or used. But some counterfeit chips still slip through, and the problem gets worse wherever there are shortages. Estimates vary widely for how much counterfeiting costs in term... » read more

NoC Obfuscation For Protecting Against Reverse Engineering Attacks (U. Of Florida)

By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks" was published by researchers at University of Florida. Abstract: "Modern System-on-Chip designs typically use Network-on-Chip (NoC) fabrics to implement coordination among integrated hardware blocks. An important class of security vulnerabilities involves a rogue foundry reverse-engineeri... » read more

U. Of Florida: Protecting Chip-Design IP From Reverse-Engineering

By Technical Paper Link - 13 Jun, 2022 - Comments: 0

New research paper titled "Hardening Circuit-Design IP Against Reverse-Engineering Attacks" from University of Florida. "Design-hiding techniques are a central piece of academic and industrial efforts to protect electronic circuits from being reverse-engineered. However, these techniques have lacked a principled foundation to guide their design and security evaluation, leading to a long line... » read more

Hardware Encryption: Ultra-compact Active Interconnect Based on FeFET

By Technical Paper Link - 02 May, 2022 - Comments: 0

New technical paper "Hardware functional obfuscation with ferroelectric active interconnects" from researchers at Penn State, Rochester Institute of Technology, GlobalFoundries Fab1, North Dakota State University. Abstract "Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we... » read more

New Security Approaches, New Threats

By Ed Sperling - 09 Dec, 2020 - Comments: 0

New and different approaches to security are gaining a foothold as the life expectancy for advanced chips increases, and as emerging technologies such as quantum computing threaten to crack even the most complex encryption schemes. These approaches include everything from homomorphic encryption, where data is processed without being decrypted, to different ways of sending and receiving data ... » read more

Scaling Anti-Tamper Protection To Meet Escalating Threats

By Scott Best - 04 Jun, 2020 - Comments: 0

Anti-tamper tends to be one of those catchall phrases encompassing any countermeasure on a security chip. A more precise definition would be that anti-tamper protection is any collection of countermeasures that serves to thwart an adversary’s attempt to monitor or affect the correct operation of a chip or a security core within a chip. Given that, it can be useful to think about a hierarchy o... » read more

IP Security In FPGAs

By Ed Sperling - 05 Sep, 2019 - Comments: 0

Quinn Jacobson, strategic architect at Achronix, talks about security in FPGAs, including how to prevent reverse engineering of IP, how to make sure the design is authentic, and how to limit access to IP in transit and in the chip. » read more

Using Run-Time Reverse-Engineering to Optimize DRAM Refresh

By Technical Paper Link - 31 Dec, 2017 - Comments: 0

Abstract: "The overhead of DRAM refresh is increasing with each density generation. To help offset some of this overhead, JEDEC designed the modern Auto-Refresh command with a highly optimized architecture internal to the DRAM---an architecture that violates the timing rules external controllers must observe and obey during normal operation. Numerous refresh-reduction schemes manually refresh ... » read more

Defending Against Reverse Engineering

By Ernest Worthman - 04 Aug, 2014 - Comments: 0

Most of us are familiar with the term “reverse engineering.” We generally know that it is used to extract data or designs from chips, but exactly how is pretty much a mystery. Today, chip security has very broad implications. The landscape of tomorrow will be cluttered with devices that are microprocessor-controlled, including some that are autonomous. Numbers vary, but the current esti... » read more

White Hat Hacking

By Ernest Worthman - 04 Aug, 2014 - Comments: 0

At first glance, the words “reverse engineering” (RE) might conjure up a couple of nefarious individuals with table full of tools, meters, and the like, in some basement trying to figure out how to disassemble some sort of electronic device. The image is wrong, however. More likely, today’s RE work will be found in a clandestine, well-funded uber-laboratory in an up-and-coming third-wo... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.