DRAM timing parameters, which should be followed during normal DRAM operations can be reduced for performing Refresh operation, and by reverse engineering those internal timing parameters at system-init time an external memory controller can use them in conjunction with individual Activate and Precharge commands, thereby reducing the performance overhead afforded Auto-Refresh, while simultaneously supporting row-by-row refresh reduction schemes.
Abstract:
“The overhead of DRAM refresh is increasing with each density generation. To help offset some of this overhead, JEDEC designed the modern Auto-Refresh command with a highly optimized architecture internal to the DRAM—an architecture that violates the timing rules external controllers must observe and obey during normal operation. Numerous refresh-reduction schemes manually refresh the DRAM row-by-row, eliminating unnecessary refreshes to improve both energy and performance of the DRAM. However, it has been shown that modern Auto-Refresh is incompatible with these schemes, that their manual refreshing of specified rows through explicit Activate and Precharge precludes them from exploiting the architectural optimizations available internally for Auto-Refresh operations.
This paper shows that various DRAM timing parameters, which should be followed during normal DRAM operations can be reduced for performing Refresh operation, and by reverse engineering those internal timing parameters at system-init time an external memory controller can use them in conjunction with individual Activate and Precharge commands, thereby reducing the performance overhead afforded Auto-Refresh, while simultaneously supporting row-by-row refresh reduction schemes.
Through physical experiments and measurement, we find that our optimized scheme reduces tRFC by up to 45% compared to the already highly-optimized Auto-Refresh mechanism. It is also 10% more energy-efficient and 50% more performance-efficient than the non-optimized row-by-row refresh. Further evaluations done by simulating future 16 Gb DDR4 devices show how the reduction in tRFC improves the application performance and energy efficiency. The proposed technique enhances all of the existing refresh-optimization schemes that use row-by-row refresh, and it does so without requiring any modification to the DRAM or DRAM protocol.”
Find the technical paper here.
Mathew, D. M., Zulian, É. F., Jung, M., Kraft, K., Weis, C., Jacob, B., & Wehn, N. (2017). Using run-time reverse-engineering to optimize DRAM refresh. Proceedings of the International Symposium on Memory Systems – MEMSYS ’17.
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