Researchers propose a “hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. “
New technical paper “Hardware functional obfuscation with ferroelectric active interconnects” from researchers at Penn State, Rochester Institute of Technology, GlobalFoundries Fab1, North Dakota State University.
Abstract
“Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks.”
Find the open access technical paper here. Published April 2022.
Yu, T., Xu, Y., Deng, S. et al. Hardware functional obfuscation with ferroelectric active interconnects. Nat Commun 13, 2235 (2022). https://doi.org/10.1038/s41467-022-29795-3.
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