CXL Picks Up Steam In Data Centers


CXL is gaining traction inside large data centers as a way of boosting utilization of different compute elements, such as memories and accelerators, while minimizing the need for additional racks of servers. But the standard is being extended and modified so quickly that it is difficult to keep up with all the changes, each of which needs to be verified and validated across a growing swath of h... » read more

Selecting The Right RISC-V Core


With an increasing number of companies interested in devices based on the RISC-V ISA, and a growing number of cores, accelerators, and infrastructure components being made available, either commercially or in open-source form, end users face an increasingly difficult challenge of ensuring they make the best choices. Each user likely will have a set of needs and concerns that almost equals th... » read more

Design And Verification Methodologies Breaking Down


Tools, methodologies and flows that have been in place since the dawn of semiconductor design are breaking down, but this time there isn't a large pool of researchers coming up with potential solutions. The industry is on its own to formulate those ideas, and that will take a lot of cooperation between EDA companies, fabs, and designers, which has not been their strong point in the past. It ... » read more

Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU (Ecole Polytechnique Montreal, IBM, Mila, CMC)


A new technical paper titled "BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU" was written by researchers at Ecole Polytechnique Montreal, IBM, Mila and CMC Microsystems. It was accepted for publication in the 2023, 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023) in Japan. Abstract: "We present a DNN accelerator that allows inference at arbitr... » read more

FPGA-Based Prototyping Framework For Processing In DRAM (ETH Zurich & TOBB Univ.)


A technical paper titled "PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM" was published by researchers at ETH Zurich and TOBB University of Economics and Technology. Abstract "Processing-using-memory (PuM) techniques leverage the analog operation of memory cells to perform computation. Several recent works have demonstrated PuM techniques in off-the-shelf DRAM dev... » read more

Week In Review: Design, Low Power


Top Of The News Google announced it will support the RISC-V architecture with the Android open-source operating system. In a keynote at the RISC-V Summit, Lars Bergstrom, Google's director of engineering for the Android Platform Programming Languages, noted that Android currently has more than 3 billion users and the support of more than 24,000 vendors. "We've been following RISC-V for a very ... » read more

Week In Review: Design, Low Power


RISC-V The European Union said it will spend the equivalent of $286.5 million on a high performance computing ecosystem based on RISC-V. According to the call for proposals, the aim of the project is to “establish a partnership between the EuroHPC JU and a consortium of industry, research organizations and institutions in HPC to the development of innovative HPC hardware and software technol... » read more

RISC-V Pushes Into The Mainstream


RISC-V cores are beginning to show up in heterogeneous SoCs and packages, shifting from one-off standalone designs toward mainstream applications where they are used for everything from accelerators and extra processing cores to security applications. These changes are subtle but significant. They point to a growing acceptance that chips or chiplets based on an open-source instruction set ar... » read more

Adapting To Broad Shifts Essential In 2022


Change creates opportunity, but not every company is able to respond quickly enough to take advantage of those opportunities. Others may respond too quickly, before they properly understand the implications. At the start of a typical year, optimism is in plentiful supply. Any positive trend is seen as continuing, and any negative is seen as turning around. Normally the later in the year that... » read more

Extending RISC-V Processors In The Field With Codasip Studio & Menta eFPGA


RISC-V is an open specification that allows an infinite number of implementations. But RISC-V goes beyond that and encourages processor architects to add new instructions to accelerate certain algorithms or application domains, for example DSP, AI/ML, and others, while keeping the base instruction set stable. The new instructions may help with the performance, code size, power consumption, or d... » read more

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