Automating Root-Cause Analysis To Reduce Time To Find Bugs by Up To 50%


If you’re spending more than 50% of your verification effort in debug, you’re not alone. For many design, verification, and embedded software engineers as well as engineers verifying complex standard protocols, debug is the primary bottleneck in verification. Most debug today is completed using the traditional methodology of print statements paired with waveforms. Given that today’s desig... » read more

Root Cause Deconvolution


Scan logic diagnosis turns failing test cycles into valuable data and is an established method for digital semiconductor defect localization. The advent of layout-aware scan diagnosis represented a dramatic advance in diagnosis technology because it reduces suspect area by up to 85% and identifies physical net segments rather than entire logic nets [1-3]. The defect classifications provided by ... » read more

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