Customizing A LLM Model For VHDL Design of High-Performance MPUs (IBM)


A new technical paper titled "Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors" was published by researchers at IBM. Abstract "The use of Large Language Models (LLMs) in hardware design has taken off in recent years, principally through its incorporation in tools that increase chip designer productivity. There has been considerable discussion about the ... » read more

RTL Optimization Via Verified E-Graph Rewriting (Intel, Imperial College London)


A technical paper titled “ROVER: RTL Optimization via Verified E-Graph Rewriting” was published by researchers at Intel Corporation and Imperial College London. Abstract: "Manual RTL design and optimization remains prevalent across the semiconductor industry because commercial logic and high-level synthesis tools are unable to match human designs. Our experience in industrial datapath des... » read more

Start Verification Early To Avoid Pitfalls Later


It is well understood – at least from a theoretical point of view – that design verification should start as early as possible. The reality is that that doesn’t always happen for a variety of reasons such as enormous time to market pressure, too many new features to add, lack of foresight and discipline among other things. But progress is being made. Harry Foster, chief scientist for v... » read more