Formal Verification of Security Properties On RTL Designs

By Technical Paper Link - 27 Jul, 2024 - Comments: 0

A technical paper titled “RTL Verification for Secure Speculation Using Contract Shadow Logic” was published by researchers at Princeton University, MIT CSAIL, and EPFL. Abstract: "Modern out-of-order processors face speculative execution attacks. Despite various proposed software and hardware mitigations to prevent such attacks, new attacks keep arising from unknown vulnerabilities. Thus... » read more

Increasing IP And SoC Debug Efficiency 10X With Intelligent Waveform Reuse

By Synopsys - 11 Jan, 2022 - Comments: 0

Design and verification reuse lies at the very heart of every modern chip development effort. A system on chip (SoC) project with billions of gates cannot possibly be completed in reasonable time without leveraging blocks from prior projects and commercial intellectual property (IP) offerings. These reused blocks are themselves challenging to develop since they are as large and complex as previ... » read more

Speeding Up Verification Using SystemC

By Ed Sperling - 23 Mar, 2020 - Comments: 0

Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

The Challenge Of RISC-V Compliance

By Brian Bailey - 28 Feb, 2019 - Comments: 0

The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that ... » read more

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tag: RTL verification

Formal Verification of Security Properties On RTL Designs

Increasing IP And SoC Debug Efficiency 10X With Intelligent Waveform Reuse

Speeding Up Verification Using SystemC

The Challenge Of RISC-V Compliance

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tag: RTL verification

Formal Verification of Security Properties On RTL Designs

Increasing IP And SoC Debug Efficiency 10X With Intelligent Waveform Reuse

Speeding Up Verification Using SystemC

The Challenge Of RISC-V Compliance

Trending Articles

Shift Left Is The Tip Of The Iceberg

Hybrid Bonding Makes Strides Toward Manufacturability

Advanced Packaging Driving New Collaboration Across Supply Chain

Chiplets Make Progress Using Interconnects As Glue

2D Semiconductors Make Progress, But So Does Silicon

Knowledge Centers Entities, people and technologies explored

Related Articles

Shift Left Is The Tip Of The Iceberg

Partitioning In The Chiplet Era

3.5D: The Great Compromise

AI’s Role In Chip Design Widens, Drawing In New Startups

Key Technologies To Extend EUV To 14 Angstroms

What Comes After HBM For Chiplets

Memory Fundamentals For Engineers

Why Small Fab And Assembly Houses Are Thriving

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