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Week In Review: Design, Low Power


Tools Andes Technology certified Imperas reference models for the complete range of Andes IP cores with the new RISC-V P SIMD/DSP extension. The reference models can be used to evaluate multicore design configuration options for SoC architecture exploration and support early software development before silicon prototypes are available. Cadence's digital full flow was optimized and certified... » read more

Week In Review: Design, Low Power


Tools & IP Cadence debuted the Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping systems. The Palladium Z2 is based on a new custom emulation processor, while the Protium X2 is based on Xilinx UltraScale+ VU19P FPGAs. Designed to work together with a common front-end flow, they provide 2X capacity and 1.5X performance improvements over the previous generations, and ne... » read more