The Early Bird Gets More Secure Hardware

By Rob van Blommestein - 02 Sep, 2021 - Comments: 0

I’m sure you’ve heard the expression “The early bird gets the worm.” This proverb emphasizes the importance of starting something early to maximize the potential outcome. In terms of hardware security, this idiom is spot on. Cybersecurity shouldn’t only be about protecting the software from attacks. Hardware is just as important. Cyberattacks continue to advance significantly, prog... » read more

Week In Review: Design, Low Power

By Jesse Allen - 16 Jul, 2021 - Comments: 0

Tools Andes Technology certified Imperas reference models for the complete range of Andes IP cores with the new RISC-V P SIMD/DSP extension. The reference models can be used to evaluate multicore design configuration options for SoC architecture exploration and support early software development before silicon prototypes are available. Cadence's digital full flow was optimized and certified... » read more

Week In Review: Design, Low Power

By Jesse Allen - 09 Apr, 2021 - Comments: 0

Tools & IP Cadence debuted the Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping systems. The Palladium Z2 is based on a new custom emulation processor, while the Protium X2 is based on Xilinx UltraScale+ VU19P FPGAs. Designed to work together with a common front-end flow, they provide 2X capacity and 1.5X performance improvements over the previous generations, and ne... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: SA-EDI

The Early Bird Gets More Secure Hardware

Week In Review: Design, Low Power

Week In Review: Design, Low Power