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Week In Review: Design, Low Power

New hardware-assisted verification systems; secure PCB manufacturing; die-to-die PHY.

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Tools & IP
Cadence debuted the Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping systems. The Palladium Z2 is based on a new custom emulation processor, while the Protium X2 is based on Xilinx UltraScale+ VU19P FPGAs. Designed to work together with a common front-end flow, they provide 2X capacity and 1.5X performance improvements over the previous generations, and new modular compile technology is capable of compiling 10 billion gates in under 10 hours on the Palladium Z2 system and in under 24 hours on the Protium X2 system. Nvidia, AMD, and Arm noted using the tools.

Synopsys unveiled the HAPS-100 prototyping system. HAPS-100 provides 20-50 MHz for complex SoCs and up to 500 MHz for interface IP, with a flexible direct connect architecture enabling a broad portfolio of HAPS interface cards, prototyping ecosystem, and IP Prototyping Kits. Additionally, the HAPS Gateway allows engineers access from anywhere and manage multi-design, multi-user deployment. Nvidia and Furiosa both noted using the solution.

Siemens launched PCBflow, a secure environment for PCB design teams to interact with a variety of manufacturers. The tool uses the Valor NPI software engine to perform a range of design-for-manufacturing (DFM) analyses in the context of each manufacturers’ process capabilities, and can sort and prioritize violations according to level of severity with guidance using images and locations of violations for identification and immediate correction. Nistec noted time and cost savings using PCBflow.

ESSS and Ansys teamed up on a discrete element modeling (DEM) workflow for analyzing and assessing particle movement across numerous industrial applications. The resulting Ansys Rocky workflow uses multiple GPUs simultaneously to analyze bulk material flow systems faster and can model particles shapes including arbitrary 3D shapes, 2D shells and flexible fiber. It is integrated with Ansys’ Fluent and Mechanical products.

OpenFive launched a Die-to-Die (D2D) PHY which, with the company’s D2D Controller, provides a D2D interface solution for various packages including substrates and interposers. The new D2D PHY helps disaggregate large SoC die into smaller smaller die. It features up to 16Gbps NRZ signals with clock forwarding architecture. Each channel, comprising of 40 IOs, can provide effective throughput of up to ~1.75Tbps/mm. Users can stack up multiple channels to further increase overall throughput. The PHY also features built-in PLL, programmable output drivers, and link training state machines.

FPGA
Stockholders of AMD and Xilinx voted to approve the acquisition of Xilinx by AMD. The deal is expected to close by the end of 2021.

Achronix began shipping its 7nm Speedster7t AC7t1500 FPGAs. It targets high bandwidth workloads in a range of applications including AI/ML, 5G infrastructure, networking, computational storage, test and measurement. It is built on TSMC’s 7nm process and includes a 2D NoC with more than 20 Tbps of bi-directional bandwidth, 112 Gbps SerDes, PCIe Gen5, 400G Ethernet, and 4 Tbps external memory bandwidth with its GDDR6 memory interfaces.

Efinix expanded its Titanium FPGA product line to include devices up to 1M logic elements (LEs). Including hardened features such as high-speed SERDES, security blocks, and MIPI interfaces, the line now spans 35K to 1M LEs and targets the cost and power sensitive mainstream markets.

Manufacturing
Synopsys’ IC Validator physical verification solution was deployed on Samsung Foundry’s SAFE Cloud Design Platform (SAFE-CDP). The platform uses HPC resources from Rescale and Microsoft Azure, providing compute resource savings of up to 30% and faster signoff.

Cadence’s digital 20.1 full flow has been optimized for Samsung Foundry’s advanced-process technologies down to 4nm. Key features include concurrent macro and standard cell placement for automated floorplanning; unified implementation, timing and IR signoff engines; ML capabilities to minimize design margins; and a common user interface and database. Example flows for HPC tasks such as concurrent macro and standard cell placement, clock mesh, balanced H Tree clock distribution, power delivery network and IR optimization are available.

An automotive-optimized Cadence digital full flow is now available for Samsung Foundry’s 14LPU process technology. The flow is tuned for automotive safety, quality, and reliability requirements and has received a Tool Confidence Level 1 (TCL1) certification. The Tensilica ConnX B10 DSP was used to validate the flow.

Standards
Accellera released a draft version of the Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0 for public review. SA-EDI aims to address security concerns for hardware and software IP by offering IP providers a standardized means to disclose relevant security properties for the integrator to consider for integration, assisting IP integrators in understanding and reducing security risk, and accelerating tool development to facilitate security assurance automation. Public review is open through May 21.

Events
Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

SEMI’s MEMS & Sensors Technical Congress will be held April 13-15. GSA’s Silicon Leadership Summit will be held April 14-15. The Linley Spring Processor Conference 2021 will take place April 19-23. On April 20-22, several events will take place: Synopsys’ SNUG World, Ansys’ Simulation World, and the Industry Strategy Symposium Europe 2021. The IEEE Custom Integrated Circuits Conference (CICC 2021) will close out the month on April 25-30.



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