tag: scan test

The Single Best DFT Move You Can Make
By Jay Jahangiri - 08 Oct, 2019 - Comments: 0

A proven method to simplify a complex problem is to break it into smaller chunks. In the case of today’s large, complex SoCs, this means using hierarchical methods to design the blocks, then combine the results at the top level. While this sounds obvious, it hasn’t always been practical or technologically feasible to perform some tasks, like DFT, at the block level and translate that work s... » read more

Scan Compression Is No Longer About Compression
By Rohit Kapur - 16 Sep, 2019 - Comments: 0

Scan compression was introduced in the year 2000 and has seen rapid adoption. Nearly every design’s test methodology today implements this technology, which inserts compression logic in the scan path between the scan I/Os and the internal chains. In this article, we take a critical look at the technology to understand how scan compression has matured. The road to scan compression Since th... » read more

Highly Efficient Scan Diagnosis With Dynamic Partitioning
By Jayant D'Souza - 10 Sep, 2019 - Comments: 0

Charged with the task of improving yield, product engineers need to find the location of defects in manufactured ICs quickly and efficiently. Typically, they use volume scan diagnosis to generate large amounts of data from failing test cycles, which is then analyzed to reveal the location of defects. Scan failure data provides the basis for many decisions in the failure analysis and yield impro... » read more

Breakthrough For Scan Diagnosis With Machine Learning
By Matthew Knowles - 07 May, 2019 - Comments: 0

Cell-aware diagnosis is a new and effective way to detect defects inside standard cells. Industry standard failure analysis (FA) results from a major foundry show that cell-aware diagnosis is very effective at increasing the resolution of the diagnosis by reducing the number of suspects in cell-internal defect data. With advanced technology nodes, we have more complex layout structures and f... » read more

Building Bridges: A New DFT Paradigm
By Robert Ruiz - 28 Mar, 2019 - Comments: 0

Over the last twenty years, structural testing with scan chains has become pervasive in chip design methodology. Indeed, it’s remarkable to think that most electronic devices we interact with today (think smartphones, laptops, televisions, etc.) contain hundreds to thousands of interconnected scan chains used to verify that the semiconductors were manufactured without defects. Because the imp... » read more

Understanding NI CompactRIO Scan Mode
By NI - 07 May, 2018 - Comments: 0

The LabVIEW Real-Time Module 8.6 introduced powerful new features for programming CompactRIO hardware that reduce development time and complexity as well as provide tools for monitoring and maintaining CompactRIO applications. This functionality is powered by two technologies in LabVIEW, the NI Scan Engine and the RIO Scan Interface. The NI Scan Engine is a new component of LabVIEW Real-Time th... » read more

Safety Plus Security: A New Challenge
By Brian Bailey - 08 Jun, 2017 - Comments: 0

Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

Fault Simulation Reborn
By Brian Bailey - 23 Feb, 2017 - Comments: 0

Fault simulation, one of the oldest tools in the EDA industry toolbox, is receiving a serious facelift after it almost faded from existence. In the early days, fault simulation was used to grade the quality of manufacturing test vectors. That task was replaced almost entirely by [getkc id="173" comment="scan test"] and automatic test pattern generation (ATPG). Today, functional safety is cau... » read more

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