tag: SCE-MI

SoC Co-Emulation Using Zynq Boards
By Michelle Mata - 27 Feb, 2020 - Comments: 0

Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome? Well, for software and hardware engineers developing an SoC, the merging of their respective engineering efforts for verification purposes is a big challenge. Early... » read more

Co-Modeling Takes Emulation To The Next Level: System-Of-Systems
By Ron Squiers - 14 Dec, 2017 - Comments: 0

As designs move beyond System-on-Chip (SoC) to more complex System-of-Systems (SoS), it’s essential for design teams to effectively verify that these systems function together as intended. Increasingly, system design companies are turning to emulators as the only verification platform with the capacity and performance to validate that their SoC and SoS designs function as intended. Today�... » read more

Using FPGAs For Emulation
By Krzysztof Szczur - 30 Nov, 2017 - Comments: 0

For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big Box” emulators and typically were used in order to recover some of the time lost on RTL simulation. Meanwhile, FPGA technology has been available long enough to mature to the point where FPGA bas... » read more

Hybrid Emulation
By Brian Bailey - 29 Jun, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Too Big To Simulate?
By Ann Mutschler - 27 Oct, 2016 - Comments: 2

With system design complexity set on a steady upward trajectory, there are situations in which traditional simulation just can’t keep up. The alternative—and one being used by Google, Uber, Ford, GM, Volvo, Audi and others with autonomous vehicles— is to test cars on the road and collect data for later analysis. “They're not simulating, they're just doing it all in the real world ... » read more

Emulation’s Footprint Grows
By Brian Bailey - 27 Oct, 2016 - Comments: 0

It wasn't that many years ago that [getkc id="30" comment="emulation"] was an expensive tool available to only a few, but it has since become indispensable for a growing number of companies. One obvious reason is the growing size of designs and the inability of [getkc id="11" kc_name="simulation"] to keep up. But emulation also has been going through a number of transformations that have made i... » read more

Why I See C In SCE-MI
By Jacek Majkowski - 24 Mar, 2016 - Comments: 0

The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are, “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”? You a probably reading this during a coffee break, so let’s jump to second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with D... » read more

Predictions For 2016: Tools and Flows
By Brian Bailey - 28 Jan, 2016 - Comments: 0

Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We beli... » read more

Say Hi To Hybrid
By Doug Amos - 29 Oct, 2015 - Comments: 0

It has been proposed for some time that virtual platforms could be linked to emulation hardware in order to co-verify the software and hardware components of an SoC. However, that proposal now has evolved into hybrid emulation, a practical solution to allow pre-silicon verification and validation of today’s complex SoC designs. First-rate work by the standards body Accellera and the Open ... » read more

UVM: What’s Stopping You?
By Doug Amos - 02 Jul, 2015 - Comments: 0

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based [gettech id="31055" comment="UVM"]. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? If UVM is as great as all that, then why hasn’t everybody adopted it already... » read more

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