Chip Industry Week In Review


By Liz Allan, Jesse Allen, and Karen Heyman. Canon uncorked a nanoimprint lithography system, which the company said will be useful down to about the 5nm node. Unlike traditional lithography equipment, which projects a pattern onto a resist, nanoimprint directly transfers images onto substrates using a master stamp patterned by an e-beam system. The technology has a number of limitations and... » read more

Blog Review: October 11


Cadence's Sangeeta Soni examines Integrity and Data Encryption (IDE) verification considerations for Compute Express Link (CXL) devices, including MAC generation and handling, key programming and exchange, and early MAC termination. Synopsys' Madhumita Sanyal points to how the increased bandwidth of PCIe 6.0 supports the demanding requirements of AI accelerators. Siemens' Kevin Webb expla... » read more

Using Smart Data To Boost Semiconductor Reliability


The chip industry is looking to AI and data analytics to improve yield, operational efficiency, and reduce the overall cost of designing and manufacturing complex devices. In fact, SEMI estimates its members could capture more than $60B in revenues associated through smart data use and AI. Getting there, however, requires overcoming a number of persistent obstacles. Smart data utilization is... » read more

Blog Review: October 4


Cadence's Felipe Goncalves checks out the Integrity and Data Encryption (IDE) feature in PCIe 6.0, a new layer inserted between the transection layer and data link layer with the goal of protecting against threats from physical attacks on the link. Siemens' Robin Bornoff, Daniel Berger, and Kai Liu explore the potential for large language models (LLMs) make the use of CAE tools simpler, more... » read more

Blog Review: September 27


Siemens' Dirk Hartmann examines how a continual improvement in predictive capability processing and algorithms enables the evolution of simulation performance and highlights two areas that underpin most simulation tools. Synopsys' Ian Land, Jason Niatas, and Marc Serughetti note that digital twins can be used from the chip level through sub-systems and up to the system level to examine perfo... » read more

Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan The U.S. Department of Defense (DOD) announced $238 million in awards toward establishing eight regional innovation hubs under the CHIPS and Science Act. The hubs aim to accelerate hardware prototyping and "lab-to-fab" transition of semiconductor technologies for secure edge/IoT, 5G/6G, AI hardware, quantum technology, electromagnetic warfare, and ... » read more

New Plasma Power Technologies For Next-Gen Semiconductor Manufacturing


As chip designs push the limits of speed, size and complexity, the semiconductor industry has set its sights on angstrom-scale device features. High-speed, precise and repeatable plasma power delivery with sophisticated controls is fundamental to process and device improvements. These factors support inflection points in technologies from chip-scale packaging through advanced front-end technolo... » read more

Blog Review: September 20


Siemens' Patrick Hope considers the unique attributes of materials used in flex and rigid-flex PCB designs and how they are constructed. Synopsys' Kenneth Larsen and Shekhar Kapoor find that the increased impact of thermal, signal integrity, and other multi-physics effects on multi-die systems calls for looking at the whole system, from technology to dies and package together. Cadence's V... » read more

Chip Industry Week In Review


By Gregory Haley, Jesse Allen, and Liz Allan TSMC told equipment vendors to delay deliveries of the most advanced tools due to uncertain demand, according to Reuters. The news drove down stock prices of all the major equipment providers. On the other hand, TSMC said advanced packaging shortages will constrain AI chip shipments for the next 18 months, according to NikkeiAsia. The United St... » read more

Blog Review: September 13


Siemens' Todd Westerhoff highlights the importance of signal integrity analysis in PCB design, challenges as simulation tools have become more sophisticated and difficult to use, and best practices like starting with a simple analysis problem. Synopsys' Rita Horner, Shekhar Kapoor, and William Ruby note that the power and thermal profiles of multi-die systems for HPC and the data center shou... » read more

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