What’s Next For Through-Silicon Vias

By Laura Peters - 06 Jan, 2025 - Comments: 0

From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

Wafer Bin Map Defect Classification Using Semi-Supervised Learning

By Technical Paper Link - 27 Dec, 2024 - Comments: 0

A new technical paper titled "Semi-Supervised Learning with Wafer-Specific Augmentations for Wafer Defect Classification" was published by researchers at Korea University. Abstract "Semi-supervised learning (SSL) models, which leverage both labeled and unlabeled datasets, have been increasingly applied to classify wafer bin map patterns in semiconductor manufacturing. These models typical... » read more

Semiconductor Engineering’s Special Reports 2024

By The SE Staff - 23 Dec, 2024 - Comments: 0

Semiconductor Engineering published 36 special reports in 2024. Focus Areas Manufacturing, Packaging, Materials Test, Measurement New Fabs and Funding Memory Design Power, Performance Manufacturing, Packaging, Materials Navigating Increased Complexity In Advanced Packaging Intel Vs. Samsung Vs. TSMC Hybrid Bonding Makes Strides Toward Manufacturability 3.5D: The Great Comp... » read more

Monolithic Vs. Heterogeneous Integration

By Ed Sperling - 24 Oct, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss two very different paths forward for semiconductors and what's needed for each, with Jamie Schaeffer, vice president of product management at GlobalFoundries; Dechao Guo, director of advanced logic technology R&D at IBM; Dave Thompson, vice president at Intel; Mustafa Badaroglu, principal engineer at Qualcomm; and Thomas Po... » read more

Review of Automatic EM Image Algorithms for Semiconductor Defect Inspection (KU Leuven, Imec)

By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Electron Microscopy-based Automatic Defect Inspection for Semiconductor Manufacturing: A Systematic Review" was published by researchers at KU Leuven and imec. Abstract: "In this review, automatic defect inspection algorithms that analyze Electron Microscope (EM) images of Semiconductor Manufacturing (SM) products are identified, categorized, and discussed. Thi... » read more

SIA’s Report On the State of the U.S. Semiconductor Industry

By Technical Paper Link - 18 Sep, 2024 - Comments: 0

The Semiconductor Industry Association released its 2024 State of the U.S. Semiconductor Industry report this week, highlighting opportunities for growth, current and emerging challenges, and relevant metrics. The report reviews the progress made on implementation of the CHIPS Act and associated manufacturing incentives. Supply chain rebalancing, workforce challenges, geopolitics and globa... » read more

Building Smarter, Better Fabs

By Laura Peters - 15 Aug, 2024 - Comments: 0

Battling labor shortages, faster ramp rates, and data overload, the process of designing and building greenfield fabs requires a combination of tech tools, failing earlier approaches and superior planning from day one. The complexity and scale of semiconductor fabs is skyrocketing as is the capital cost. Chipmakers are looking to ramp multibillion dollar fabs faster despite the hurdles of la... » read more

CHIPS For America’s National Semiconductor Technology Center (NSTC) Program

By Barry Pangrle - 03 Jul, 2024 - Comments: 0

At this year’s Design Automation Conference, Jay Lewis, director of CHIPS for America National Semiconductor Technology Center (NSTC) Program, gave a presentation on the status and direction of the Center, its priorities for this year and how the NSTC can change the long-term trajectory for innovation. Fig. 1: Dr. Jay Lewis, director of NSTC Program, CHIPS R&D Office at the Dept. o... » read more

Cyber Threats To The SECS/GEM Protocol In Smart Manufacturing

By YenTing Lee - 02 Jul, 2024 - Comments: 0

Semiconductors are an indispensable part of modern electronic products and are also a fundamental basis for the development of the AI industry. This industry is crucial for global economic growth and national security. As the semiconductor industry transitions to Industry 4.0, the connection between production equipment and factory networks has expanded the attack surface, providing adversaries... » read more

Making Adaptive Test Work Better

By Ed Sperling - 10 Jun, 2024 - Comments: 0

One of the big challenges for IC test is making sense of mountains of data, a direct result of more features being packed onto a single die, or multiple chiplets being assembled into an advanced package. Collecting all that data through various agents and building models on the tester no longer makes sense for a couple reasons — there is too much data, and there are multiple customers using t... » read more

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tag: semiconductor manufacturing

What’s Next For Through-Silicon Vias

Wafer Bin Map Defect Classification Using Semi-Supervised Learning

Semiconductor Engineering’s Special Reports 2024

Monolithic Vs. Heterogeneous Integration

Review of Automatic EM Image Algorithms for Semiconductor Defect Inspection (KU Leuven, Imec)

SIA’s Report On the State of the U.S. Semiconductor Industry

Building Smarter, Better Fabs

CHIPS For America’s National Semiconductor Technology Center (NSTC) Program

Cyber Threats To The SECS/GEM Protocol In Smart Manufacturing

Making Adaptive Test Work Better

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Baby Steps Toward 3D DRAM

What’s Next For Through-Silicon Vias

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Navigating Increased Complexity In Advanced Packaging

Knowledge Centers
Entities, people and technologies explored