Monolithic Vs. Heterogeneous Integration

By Ed Sperling - 24 Oct, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss two very different paths forward for semiconductors and what's needed for each, with Jamie Schaeffer, vice president of product management at GlobalFoundries; Dechao Guo, director of advanced logic technology R&D at IBM; Dave Thompson, vice president at Intel; Mustafa Badaroglu, principal engineer at Qualcomm; and Thomas Po... » read more

Review of Automatic EM Image Algorithms for Semiconductor Defect Inspection (KU Leuven, Imec)

By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Electron Microscopy-based Automatic Defect Inspection for Semiconductor Manufacturing: A Systematic Review" was published by researchers at KU Leuven and imec. Abstract: "In this review, automatic defect inspection algorithms that analyze Electron Microscope (EM) images of Semiconductor Manufacturing (SM) products are identified, categorized, and discussed. Thi... » read more

SIA’s Report On the State of the U.S. Semiconductor Industry

By Technical Paper Link - 18 Sep, 2024 - Comments: 0

The Semiconductor Industry Association released its 2024 State of the U.S. Semiconductor Industry report this week, highlighting opportunities for growth, current and emerging challenges, and relevant metrics. The report reviews the progress made on implementation of the CHIPS Act and associated manufacturing incentives. Supply chain rebalancing, workforce challenges, geopolitics and globa... » read more

Building Smarter, Better Fabs

By Laura Peters - 15 Aug, 2024 - Comments: 0

Battling labor shortages, faster ramp rates, and data overload, the process of designing and building greenfield fabs requires a combination of tech tools, failing earlier approaches and superior planning from day one. The complexity and scale of semiconductor fabs is skyrocketing as is the capital cost. Chipmakers are looking to ramp multibillion dollar fabs faster despite the hurdles of la... » read more

CHIPS For America’s National Semiconductor Technology Center (NSTC) Program

By Barry Pangrle - 03 Jul, 2024 - Comments: 0

At this year’s Design Automation Conference, Jay Lewis, director of CHIPS for America National Semiconductor Technology Center (NSTC) Program, gave a presentation on the status and direction of the Center, its priorities for this year and how the NSTC can change the long-term trajectory for innovation. Fig. 1: Dr. Jay Lewis, director of NSTC Program, CHIPS R&D Office at the Dept. o... » read more

Cyber Threats To The SECS/GEM Protocol In Smart Manufacturing

By YenTing Lee - 02 Jul, 2024 - Comments: 0

Semiconductors are an indispensable part of modern electronic products and are also a fundamental basis for the development of the AI industry. This industry is crucial for global economic growth and national security. As the semiconductor industry transitions to Industry 4.0, the connection between production equipment and factory networks has expanded the attack surface, providing adversaries... » read more

Making Adaptive Test Work Better

By Ed Sperling - 10 Jun, 2024 - Comments: 0

One of the big challenges for IC test is making sense of mountains of data, a direct result of more features being packed onto a single die, or multiple chiplets being assembled into an advanced package. Collecting all that data through various agents and building models on the tester no longer makes sense for a couple reasons — there is too much data, and there are multiple customers using t... » read more

TSMC Uncorks A16 With Super Power Rail

By Barry Pangrle - 25 Apr, 2024 - Comments: 0

TSMC showed off its forthcoming A16 process technology node, targeted for the second half of 2026, at its 30th North American Technology Symposium this week. As the foundry moves from nanometer to angstrom process numbering, the new nodes will be prefixed with an “A” designation (instead of “N”) and A16 is the first for TSMC. TSMC said that N2 is still tracking to a 2025 production s... » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing

By eBeam Initiative - 17 Apr, 2024 - Comments: 0

How Advantest Corporation, ASML, Fraunhofer, imec, Siemens EDA and others are using deep learning in semiconductor manufacturing. Click here to read more. » read more

Navigating Design Challenges

By Siemens EDA - 28 Mar, 2024 - Comments: 0

Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop v... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?