Rethinking Manufacturing Models


The perennial uncertainty surrounding EUV lithography and complications stemming from the most advanced nodes are creating a domino effect across the semiconductor industry. Rather than stalling the market, though, which is what happened with the transition to 20nm, vendors now are accelerating their product rollouts and adjusting business plans to capitalize on those delays. That includes m... » read more

The Fill Ecosystem Evolves Again


Several years ago, we wrote about the ecosystem of fill, and how 20nm technology required a much tighter relationship between the foundry, designers and EDA vendors. While the players remain the same, there have been some interesting shifts in fill techniques and usage as designers move to even-smaller technologies. What continues with each node is the additional complexity of the design flo... » read more

Shift Left: Software Or Hardware?


A couple of weeks ago I was with a virtual prototyping user who described the benefits his company has seen from deploying virtual prototyping for early software development. The use of virtual prototyping has been rolled out progressively to more projects over the years, making it possible for the company to measure its impact on the software availability schedule and the impact has been drama... » read more

Problems Ahead for EDA


Semiconductor Engineering sat down with [getperson id="11411" comment="Bill Neifert"], chief technology officer at [getentity id="22521" comment="Carbon Design Systems"]; [getperson id="11032" comment="Simon Davidmann”], chief executive officer for [getentity id="22036" e_name="Imperas”]; Randy Smith, vice president of marketing for [getentity id="22605" e_name="Sonics"] and Michel Courtoy,... » read more

Pressure Builds To Revamp The Design Flow


Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

Does Fast Simulation Help Debug Productivity?


It is nice when a reporter manages to get the scoop of the century, and that was the case at a lunch panel hosted by [getentity id="22032" e_name="Cadence"] at the recent Design and Verification Conference (DVCon) in Santa Clara, CA. Brian Bailey, technology editor for Semiconductor Engineer was the moderator for the panel and broke the news to the crowd. Cadence had developed a logic [getkc id... » read more

One-To-Many: Shifting Left, Adding Gears


[getperson id="11034" comment="Aart de Geus"], chairman and co-CEO of [getentity id="22035" e_name="Synopsys"], launched into high gear for his keynote talk at this year’s Design and Verification Conference (DVCon). The gathering attracted a record number of attendees, and it is estimated that about 350 people crammed into the room to listen to him talk about the shift left that is happening ... » read more

First Time Success And Cost Control


First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

Who Pays For EDA Shift Left?


While working on the predictions articles for 2015 (markets, design, semiconductors, tools and flows), a number of companies talked about the great shift left that is happening in the industry. What was surprising was the number of companies that mentioned it, and in very different ways. It is clear that shift left does not mean the same thing to all people. While they all see it addressing ... » read more

Bigger Systems, Bigger Profits


Markets work in very mysterious ways. Technology that should be a slam dunk—think 2.5D with its promise of re-usable analog IP and faster performance, for example—are still hobbling along because no one wants to deal with the risk of a new architectural and manufacturing approach. They haven't even shown up yet in servers, where price is almost irrelevant. At the same time (no pun intended)... » read more

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