中文 English

FICS Research Institute: Detailed Assessment of the PQC Candidates To Power Side Channel Attacks


New research paper by a team of researchers from FICS Research Institute titled "PQC-SEP: Power Side-Channel Evaluation Platform for Post-Quantum Cryptography Algorithms." Abstract "Research in post-quantum cryptography (PQC) aims to develop cryptographic algorithms that can withstand classical and quantum attacks. The recent advance in the PQC field has gradually switched from the theory t... » read more

A Low-Power BLS12-381 Pairing Cryptoprocessor for Internet-of-Things Security Applications


Abstract: "We present the first BLS12-381 elliptic-curve pairing cryptoprocessor for Internet-of-Things (IoT) security applications. Efficient finite-field arithmetic and algorithm-architecture co-optimizations together enable two orders of magnitude energy savings. We implement several countermeasures against timing and power side-channel attacks. Our cryptoprocessor is programmable to provid... » read more

A high speed processor for elliptic curve cryptography over NIST prime field


Abstract "Elliptic curve cryptography (ECC), as one of the public key cryptography systems, has been widely applied to many security applications. It is challenging to implement a scalar multiplication (SM) operation which has the highest computational complexity in ECC. In this study, we propose a hardware processor which achieves high speed and high security for ECC. We first present a three... » read more

Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications


Abstract: "The RowHammer vulnerability in DRAM is a critical threat to system security. To protect against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips rely on undocumented, proprietary, on-die mitigations, commonly known as Target Row Refresh (TRR). At a high level, TRR detects and refreshes potential RowHammer-victim rows, but its exact are not openly disclose... » read more

HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment


Summary "To ensure secure and trustworthy execution of applications, vendors frequently embed trusted execution environments into their systems. Here, applications are protected from adversaries, including a malicious operating system. TEEs are usually built by integrating protection mechanisms directly into the processor or by using dedicated external secure elements. However, both of these... » read more

Database Reconstruction from Noisy Volumes: A Cache Side-Channel Attack on SQLite


Authors: Aria Shahverdi, University of Maryland; Mahammad Shirinov, Bilkent University; Dana Dachman-Soled, University of Maryland Abstract: "We demonstrate the feasibility of database reconstruction under a cache side-channel attack on SQLite. Specifically, we present a Flush+Reload attack on SQLite that obtains approximate (or "noisy") volumes of range queries made to a private database... » read more

Building A More Secure SoC


SoC integrators know that a software-only chip security plan leaves devices open to attack. All that a hacker needs to do is find a way to replace key parts of the bootloader or the low-level firmware to compromise other software in the system used to support secure access. The most simple attacks come remotely over a network, and these can be patched with software upgrades. However, we see ... » read more

What Makes A Chip Tamper-Proof?


The cyber world is the next major battlefield, and attackers are busily looking for ways to disrupt critical infrastructure. There is widespread proof this is happening. “Twenty-six percent of the U.S. power grid was found to be hosting Trojans," said Haydn Povey, IAR Systems' general manager of embedded security solutions. "In a cyber-warfare situation, that's the first thing that would b... » read more