Comparing Leakage Detection Methods On RISC-V Cores (Radboud University)

A technical paper titled “Plan your defense: A comparative analysis of leakage detection methods on RISC-V cores” was published by researchers at Radboud University. Abstract: "Hardening microprocessors against side-channel attacks is a critical aspect of ensuring their security. A key step in this process is identifying and mitigating “leaky” hardware modules, which inadvertently lea... » read more

Side-Channel Security Analysis of Intel Optane Persistent Memory

A new technical paper titled "Side-Channel Attacks on Optane Persistent Memory" was published by researchers at University of Virginia, Cornell University, and Graz University of Technology. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "There is a constant evolution of technology for cloud environments, including the development of new memory storage tech... » read more

Security-Aware Compiler-Assisted Countermeasure to Mitigate Fault Attacks on RISC-V

A new technical paper titled "CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V" was published by researchers at TU Munich and Fraunhofer Institute for Applied and Integrated Security (AISEC). Abstract "Fault-injection attacks are a risk for any computing system executing security-relevant tasks, such as a secure boot process. While ha... » read more

HW-SW Co-Design Solution For Building Side-Channel-Protected ML Hardware

A technical paper titled "Hardware-Software Co-design for Side-Channel Protected Neural Network Inference" was published (preprint) by researchers at North Carolina State University and Intel. Abstract "Physical side-channel attacks are a major threat to stealing confidential data from devices. There has been a recent surge in such attacks on edge machine learning (ML) hardware to extract the... » read more

Side-Channel Attacks Via Cache On the RISC-V Processor Configuration

A technical paper titled "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment" was published by researchers at University of Electro-Communication, Academy of Cryptography Techniques, Technology Research Association of Secure IoT Edge Application based on RISC-V Open Architecture (TRASIO), and AIST. "This work proposed a cross-process exploitation ... » read more

Hertzbleed: A New Family of Side-Channel Attacks–Root Case: Dynamic Frequency Scaling

  New research paper titled "Hertzbleed: Turning Power Side-Channel Attacks Into Remote Timing Attacks on x86" from researchers at UT Austin, University of Illinois Urbana-Champaign (UIUC) and University of Washington can be found here. (preprint). This paper will be presented at the 31st USENIX Security Symposium (Boston, 10–12 August 2022). Summary explanation of the Hertzbleed ... » read more

FICS Research Institute: Detailed Assessment of the PQC Candidates To Power Side Channel Attacks

New research paper by a team of researchers from FICS Research Institute titled "PQC-SEP: Power Side-Channel Evaluation Platform for Post-Quantum Cryptography Algorithms." Abstract "Research in post-quantum cryptography (PQC) aims to develop cryptographic algorithms that can withstand classical and quantum attacks. The recent advance in the PQC field has gradually switched from the theory t... » read more

A Low-Power BLS12-381 Pairing Cryptoprocessor for Internet-of-Things Security Applications

Abstract: "We present the first BLS12-381 elliptic-curve pairing cryptoprocessor for Internet-of-Things (IoT) security applications. Efficient finite-field arithmetic and algorithm-architecture co-optimizations together enable two orders of magnitude energy savings. We implement several countermeasures against timing and power side-channel attacks. Our cryptoprocessor is programmable to provid... » read more

A high speed processor for elliptic curve cryptography over NIST prime field

Abstract "Elliptic curve cryptography (ECC), as one of the public key cryptography systems, has been widely applied to many security applications. It is challenging to implement a scalar multiplication (SM) operation which has the highest computational complexity in ECC. In this study, we propose a hardware processor which achieves high speed and high security for ECC. We first present a three... » read more

Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications

Abstract: "The RowHammer vulnerability in DRAM is a critical threat to system security. To protect against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips rely on undocumented, proprietary, on-die mitigations, commonly known as Target Row Refresh (TRR). At a high level, TRR detects and refreshes potential RowHammer-victim rows, but its exact are not openly disclose... » read more

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